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The DP80390XP is a high-performance embedded controller IP core that caters primarily to 8-bit applications, designed as a single-chip solution capable of handling both fast on-chip and slower off-chip memories. This soft core surpasses the original 80C51 architecture, providing processing speeds as much as 15.55 times faster than its predecessor while featuring particularly accelerated multiplication capabilities up to 24 times faster than conventional models. The core is engineered for enhanced computational throughput, ensuring quick execution of complex instructions, thereby offering a substantial boost in performance for embedded systems. It targets applications necessitating speed and reliability, serving as an ideal technology in environments where these qualities are paramount. In addition to its performance advantages, the DP80390XP is versatile and can be integrated across various platforms and systems. Its improved architecture ensures it remains a competitive option in scenarios demanding high-speed data processing, response reliability, and seamless execution of embedded instructions.
The DAES is a sophisticated cryptographic co-processor IP designed to implement the Rijndael encryption algorithm, which forms the basis of the Advanced Encryption Standard (AES). By supporting key sizes of both 128 and 256 bits, this core provides robust encryption capabilities through various cipher modes including ECB, CBC, CFB, OFB, and CTR, ensuring diverse applications can leverage these functionalities for enhanced data security. The DAES core is equipped with an internal key expansion module, allowing it to manage encryption and decryption operations efficiently. It offers seamless integration into APB, AHB, and AXI buses, enabling it to be easily incorporated into a wide variety of digital solutions where encryption is paramount. This IP core is adaptable, providing developers with a reliable and scalable solution to safeguard sensitive data across multiple platforms and environments. The DAES benefits sectors that heavily rely on encryption for secure transactions and communications, making it a valuable asset in industries like finance, government, and telecommunications.
The DSHA2-512 core specializes in the SHA2-512 hashing algorithm, providing a highly efficient means to process hashing functions in data-intensive environments. It is designed to comply with FIPS PUB 180-4 standards, ensuring that it meets established guidelines for secure hashing operations necessary in a variety of industry settings. With interfaces that include APB, AHB, and AXI, the DSHA2-512 exhibits broad compatibility with existing digital infrastructures, enabling it to be deployed across a wide array of technology solutions. This core is ideal for sectors where ensuring data integrity and authenticity is critical, such as finance, governmental, and secure communications sectors. Its enhanced technical capabilities mean that the DSHA2-512 core supports extensive data processing requirements while maintaining the security integrity of hashes, making it an essential component for applications that demand reliable hash computation and data security.
The DSHA2-256 core is a dedicated solution for hashing functions, specifically designed to excel in processing the SHA2-256 algorithm. Compliant with the FIPS PUB 180-4 standards, this universal core accelerates the hash operation, providing efficient and secure data processing options for diverse digital systems. Its architecture supports both APB, AHB, and AXI bus interfaces, allowing for easy integration into numerous applications that require robust hashing mechanisms. The core enhances processing capabilities, facilitating the rapid execution of secure hash functions that protect data integrity and authenticity. This IP core is invaluable in fields where data security and integrity are critical, such as banking, digital communication, and any networked environment where information verification is necessary. By providing dedicated hardware for hashing tasks, it ensures high levels of data protection and performance, making it an ideal choice for developers looking to implement reliable security solutions.
The DSHA2-384 core is optimized for executing the SHA2-384 hash function, ensuring secure and efficient handling of hashing operations within digital systems. It fully complies with FIPS PUB 180-4 standards, ensuring adherence to widely recognized security protocols and making it ideal for industries that demand high standards of data protection. This IP core supports a variety of bus interfaces including APB, AHB, and AXI, providing compatibility with a broad range of system architectures. Its advanced security features enhance hashing processes, enabling rapid and secure management of data in applications that range from financial transactions to complex data security implementations. For security-focused applications, the DSHA2-384 core offers unmatched reliability and performance. It suits environments where data integrity is paramount, supporting industries that need robust digital security measures. The core facilitates secure communications and encrypted storage, making it a vital tool for safeguarding sensitive information in a digital-first world.
The D32PRO is a versatile 32-bit processor that offers an exceptional balance between power efficiency and computational performance, benefiting systems that demand rapid processing in a compact form factor. This processor is royalty-free and silicon-proven, capable of achieving performance rates of up to 1.52/2.67 DMIPS per MHz, accommodating the needs of power-sensitive applications and modern electronic devices. Its design emphasizes increased code density, making it well-suited for modern connected devices that require efficient memory utilization. The D32PRO's scalable architecture and customizable features make it an adaptable choice for a variety of applications, ranging from consumer electronics to complex industrial systems. Given its flexibility and robust performance, this processor core supports a wide array of deployments. It enables developers to tailor its operation to specific project needs, facilitating the implementation of efficient and highly performing processors within large-scale systems as well as smaller, bespoke devices.
The DF6808 is a sophisticated 8-bit microcontroller unit (MCU) IP core with advanced on-chip peripheral capabilities, designed to efficiently handle various processing tasks. Binary-compatible with the Motorola 68HC08, this core is customizable to suit various application needs. It demonstrates significant performance improvements, operating at speeds 3.2 times faster than the original counterpart. This core supports a vast range of applications due to its efficiency and adaptability. It is equipped to manage intricate operations within embedded systems, aiding in the development of faster and more efficient devices. The DF6808 excels in environments where reliability and speed are critical, offering a robust solution for modern technology demands. The IP's design integrates seamlessly with existing architectures, providing quick deployment in a wide array of systems. With its advanced features, it is also well-suited for situations requiring detailed processing and control, making it an ideal choice for a variety of technological applications.
DRV32IMZicsr – Scalable RISC-V Power. Tailored for Your Project. Ready for the Future. The DRV32IMZicsr is a high-performance, 32-bit RISC-V processor core, equipped with M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug support. Built as part of DCD’s latest DRVX Core Family, it delivers the full flexibility, openness, and innovation that RISC-V promises—without locking you into proprietary architectures. ✅ Why RISC-V? RISC-V is a rapidly growing open standard for modern computing—backed by a global ecosystem of developers and vendors. It brings: * Freedom from licensing fees and vendor lock-in * Scalability from embedded to high-performance systems * Customizability with standard and custom instruction sets * Strong toolchain & ecosystem support 🚀 DRV32IMZicsr Highlights: * Five-stage pipeline and Harvard architecture for optimized performance * Configurable memory architecture: size and address allocation tailored to your needs Performance metrics: * **Up to 1.15 DMIPS/MHz** * **Up to 2.36 CoreMark/MHz** * Minimal footprint starting from just 14k gates * Flexible interfaces: Choose from AXI, AHB, or native bus options 🛡️ Designed for Safety & Integration: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Fully technology-agnostic, compatible with all FPGA and ASIC platforms * Seamless integration with DCD’s rich portfolio of IPs: DMA, SPI, UART, PWM, CAN, and more 🔍 Advanced Feature Set: * 32 general-purpose registers * Support for arithmetic, logic, load/store, conditional and unconditional control flow * M extension enables efficient integer multiplication/division * Zicsr extension provides robust interrupt and exception handling, performance counters, and timers * External Debug via JTAG: compliant with RISC-V Debug Specification 0.13.2 and 1.0.0, compatible with all mainstream tools 🧪 Developer-Ready: * Delivered with a fully automated testbench * Includes a comprehensive validation test suite for smooth integration into your SoC flow Whether you're building for automotive, IoT, consumer electronics, or embedded systems, the DRV32IMZicsr offers a future-ready RISC-V solution—highly configurable, performance-optimized, and backed by DCD’s 25 years of experience. Interested? Let’s build the next generation together. 📩 Contact us at info@dcd.pl
DCAN XL redefines data communication by bridging the performance gap between CAN FD and 100Mbit Ethernet, setting a new benchmark in high-speed, flexible connectivity. With data rates up to 20 Mbit/s and payloads reaching 2048 bytes, it delivers unprecedented throughput—far beyond traditional CAN standards. Engineered for versatility, DCAN XL supports advanced protocol layering and Ethernet frame tunneling, making it an ideal choice for future-proof automotive, industrial, and IoT applications. It retains the robustness and reliability of the CAN protocol while offering full backward compatibility with Classical CAN, CAN FD, and CAN XL—ensuring effortless integration into existing systems. For physical layer connectivity, DCAN XL interfaces seamlessly with standard CAN transceivers (sub-10Mbps) and CAN SIC XL transceivers (above 10Mbps), providing flexibility without compromise. It’s not just evolution—it’s the next revolution in controller area networking.
The D68000-BDM soft core is binary-compatible with an industry-standard 68000 32-bit microprocessor. It has a 16-bit data bus and a 24-bit address data bus. Of course, the code is compatible with MC68008, upward compatible with MC68010 virtual extensions, and MC68020 32-bit implementation of the architecture. Our efficient IP Core has an improved instruction set, which allows the execution of the program with higher performance than a standard 68000 core. The D68000-BDM comes with a fully automated test bench and a complete set of tests, allowing for easy package validation at each stage of the SoC design flow. A special testing platform has been built to run D68000-BDM with the uCLinux Operating System. The main goal of using uCLinux was to show that the D68000 microprocessor IP Core is fully functional and well validated. The hardware and software combination creates a very useful and flexible platform with the D68000 IP Core as the main processor. All DCD’s IP Cores are technology agnostic, ensuring 100% compatibility with all FPGA and ASIC vendors.
The D68000-CPU32 soft core is binary-compatible with the industry standard 68000's CPU32 version of the 32-bit microcontroller. The D68000-CPU32 has a 16-bit data bus and a 24-bit address data bus, and it is code compatible with the 68000's CPU32 (version of MC68020). The D68000-CPU32 includes an improved instruction set, allowing for higher performance than the standard 68000 core, and a built-in DoCD-BDM debugger interface. It is delivered with a fully automated test bench and a set of tests enabling easy package validation during different stages of the SoC design flow. The D68000-CPU32 is technology-agnostic, ensuring compatibility with all FPGA and ASIC vendors.
Digital Core Design presents the D68000-CPU32+, a soft core microprocessor compatible with the 68000's CPU32+ architecture. With a 32-bit data bus and address bus, this core is optimized for high performance program execution and includes a built-in DoCD-BDM debugger interface, making it ideal for debugging complete SoC systems. Its support for 8-, 16-, and 32-bit unaligned/aligned data-bus transfers and a vast array of addressing modes offers flexibility in complex application development. Designed for universal compatibility across FPGA and ASIC vendors, the D68000-CPU32+ is delivered with a comprehensive suite of testbenches, automatic validation tests, and sculpted documentation. The architecture boasts advanced arithmetic and logic capabilities, making it suitable for a wide array of applications, from embedded systems to complex SoCs. With licensing methods streamlined for ease of access, utilizing the D68000-CPU32+ in various contexts is both simple and efficient.
The D68000-CPU32+ soft core is binary-compatible with the industry standard 68000’s CPU32+ version of the 32-bit microcontroller. The D68000-CPU32+ has a 32-bit data bus and a 32-bit address data bus. It is code compatible with the 68000’s CPU32+ (version of MC68020). The core includes an improved instruction set, which allows program execution with higher performance than the standard 68000 core. It contains a built-in DoCD-BDM debugger interface and is delivered with a fully automated test bench, ensuring easy validation at each stage of the SoC design flow. It supports software compatibility, on-chip debugging, unaligned/aligned data-bus transfer, and various addressing and data modes. The IP Core is designed to be technology agnostic, ensuring compatibility across all FPGA and ASIC platforms.
The D6802 is an 8-bit MPU IP Core – synthesizable and fully compatible with the Motorola MC6802. It can be used as a direct replacement for the MC6802 Microprocessor. Two software-controlled power-saving modes – WAIT and HALT are available to preserve additional power. These modes make the D6802 IP Core especially attractive for automotive and battery-driven applications. It is fully customizable – delivered in the exact configuration, to meet your requirements. There is no need to pay extra for unused features and wasted silicon. The D6802 comes with a fully automated test bench with a complete set of tests, allowing easy package validation at each stage of the SoC design flow. Each DCD’s D68XX Core has built-in support for a proprietary Hardware Debug System – DoCD™. It is a real-time hardware debugger that provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of running applications. It can halt, run, step into or skip instruction and read/write any contents of the microprocessor. ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.
The D6803 is a synthesizable SOFT Microcontroller IP Core, fully compatible with the Motorola MC6803. It can be used as a direct replacement for MC6803 Microcontrollers. In the standard configuration, the core has major peripheral functions integrated on-chip. An asynchronous serial communications interface (SCI) is included, as well as the main 16-bit, three-function programmable timer. A software- controlled power-saving mode – WAIT is available to save additional power. This mode makes the D6803 IP Core especially attractive for automotive and battery-driven applications. DCD’s IP Core is fully customizable – delivered in the exact configuration to meet your requirements. There is no need to pay extra for unused features and wasted silicon. The IP Core comes with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of the SoC design flow. It has built-in support for DCD’s Hardware Debug System called DoCD™ – it is a real-time hardware debugger that provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, and read/write any contents of the microcontroller, including all registers, internal, external, and program memories, as well as user defined peripherals. Hardware breakpoints can be easily set and controlled. The IP is delivered in HDL source code, suitable for both ASIC and FPGA projects.
The D6803 is a synthesizable SOFT Microcontroller IP Core, fully compatible with the Motorola MC6803. It can be used as a direct replacement for MC6803 Microcontrollers. In the standard configuration, the core has major peripheral functions integrated on-chip. An asynchronous serial communications interface (SCI) is included, as well as the main 16-bit, three-function programmable timer. A software-controlled power-saving mode – WAIT is available to save additional power. This mode makes the D6803 IP Core especially attractive for automotive and battery-driven applications. DCD’s IP Core is fully customizable – delivered in the exact configuration to meet your requirements. There is no need to pay extra for unused features and wasted silicon. The IP Core comes with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of the SoC design flow. It has built-in support for DCD’s Hardware Debug System called DoCD™ – a real-time hardware debugger that provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, and read/write any contents of the microcontroller, including all registers, and SFRs, including user-defined peripherals and data and program memories. ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.
The D68HC11E is a synthesizable SOFT Microcontroller IP Core, fully compatible with the Motorola 68HC11E industry standard. It can be used as a direct replacement for: 68HC11E Microcontrollers and older 68HC11E versions: 68HC11A and 68HC11D In a standard configuration of the core, major peripheral functions are integrated on-chip. An asynchronous serial communications interface (SCI) and separate synchronous serial peripheral interface (SPI) are included. The main 16-bit, free-running timer system contains input capture and output- compare lines and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods. Self-monitoring and on-chip circuitry is included to protect the D68HC11E against system errors. The Computer Operating Properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt if an illegal opcode is detected. Two software-controlled power- saving modes – WAIT and STOP are available to preserve additional power. These modes make the D68HC11E IP Core especially attractive for automotive and battery-driven applications. The D68HC11E Microcontroller Core can be equipped with an ADC Controller, which allows using an external ADC Controller with standard ADC software. The ADC Controller makes external ADCs visible as internal ADCs in original 68HC11E Microcontrollers. The D68HC11E is fully customizable – it is delivered in the exact configuration to meet your requirements. There is no need to pay extra for unused features and wasted silicon. The D68HC11E comes with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of the SoC design flow. Each DCD’s D68HC11E Core has built-in support for DCD’s Hardware Debug System called DoCD™. It is a real-time hardware debugger that provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ allows non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, and read/write any contents of the microcontroller, including all registers, and SFRs, including user-defined peripherals, data, and program memories. All DCD’s IP cores are technology agnostic, ensuring 100% compatibility with all FPGA and ASIC vendors.
The D68HC11F is a synthesizable SOFT Microcontroller IP Core, fully compatible with the Motorola 68HC11F1 industry standard. It can be used as a direct replacement for the 68HC11F1 Microcontrollers. Major peripheral functions are integrated on-chip, including an asynchronous serial communications interface (SCI) and a synchronous serial peripheral interface (SPI). The main 16-bit, free-running timer system includes input capture and output-compare lines, and a real-time interrupt function. An 8-bit pulse accumulator subsystem counts external events or measures external periods. Self-monitoring on-chip circuitry protects the D68HC11F against system errors. The Computer Operating Properly (COP) watchdog system and illegal opcode detection circuit provide extra security features. Two power-saving modes, WAIT and STOP, make the IP core especially attractive for automotive and battery-driven applications. Additionally, the D68HC11F can be equipped with an ADC Controller, offering compatibility with external ADCs. Its customizable nature means it's delivered in configurations tailored to need, avoiding unnecessary features and silicon waste. The D68HC11F also includes a fully automated test bench and comprehensive tests for easy SoC design validation. It supports DCD’s DoCD™, a real-time hardware debugger, for non-intrusive debugging of complete SoCs. This IP Core is technology agnostic, ensuring 100% compatibility with all FPGA and ASIC vendors.
The D68HC11K is a synthesizable soft IP Core Microcontroller, fully compatible with the industry standard. It can be used as a direct replacement for the following Motorola MC68HC11K microcontrollers: MC68HC11K0, MC68HC11K1, MC68HC11K4, MC68HC711K4, MC68HC11KS2, MC68HC711KS2. In a standard configuration of the core, major peripheral functions are integrated on-chip. An asynchronous serial communication interface (SCI) and a separate synchronous serial peripheral interface (SPI) are included. The main 16-bit, free-running timer system contains input capture and output-compare lines and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods. The memory expansion unit (with six address extension lines) allows up to sixteen 32K byte banks of external memory to be addressed in either of two bank windows, up to 1MB. Features like self-monitoring on-chip circuitry protect against system errors. Two power-saving modes, WAIT and STOP, are especially attractive for automotive and battery-driven applications. The D68HC11K can optionally include an ADC Controller for external ADC integration. The IP is fully customizable, delivering an exact configuration to meet user requirements. It includes a comprehensive automated test bench, set of tests, and is compatible with DCD’s DoCD™ real-time hardware debugger for non-intrusive debugging. The D68HC11K is technology agnostic, ensuring compatibility with all FPGA and ASIC vendors.
The D68HC11K is a synthesizable soft IP Core Microcontroller, fully compatible with the industry standard. It can be used as a direct replacement for the Motorola MC68HC11K microcontrollers, integrating major peripheral functions on-chip. This includes an asynchronous serial communication interface (SCI), a synchronous serial peripheral interface (SPI), a main 16-bit free-running timer system with input capture, output compare lines, and a real-time interrupt function. The sub-system also includes an 8-bit pulse accumulator. The memory expansion unit permits up to sixteen 32K byte banks of external memory to be addressed, expanding the memory space up to 1MB. It features self-monitoring circuitry for protection against system errors and has a COP watchdog for software failure protection. Its two software-controlled power-saving modes make it ideal for automotive and battery-driven applications. Additionally, the D68HC11K can be equipped with an external ADC Controller to use external ADCs as internal components. It is fully customizable, allowing configurations tailored to customer requirements. The IP core comes with a comprehensive set of tests and an automated test bench for easy validation. It is fully synthesizable and compatible with all FPGA and ASIC vendors, thereby ensuring its wide applicability across different platforms and systems.
The DF6802 is an 8-bit synthesizable MPU IP Core, software-compatible with Motorola MC6802. It features an enhanced internal architecture for approximately 4 times faster execution than the original 6802 chip at the same clock frequency. Designed with two power-saving modes (WAIT and HALT), the DF6802 is ideal for automotive and battery-driven applications. It is fully customizable, allowing for a configuration that meets specific user needs, without extra costs for unused features. The IP Core comes equipped with a fully automated testbench and a comprehensive set of test cases for smooth package validation. Moreover, the DF6802 supports DCD’s Hardware Debug System, DoCD™, which offers real-time, non-intrusive debugging across the entire SoC, including the ability to halt, run, step into, or skip instructions, and read/write data to any part of the microprocessor. With support for a wide range of interfaces such as USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, and Smart Card, the DF6802 shows versatile connectivity while ensuring efficient power and performance optimization. The DF6802 is technology agnostic, ensuring compatibility with all FPGA and ASIC vendors. It comes with extensive deliverables including synthesizable RTL, testbench environment, simulation macros, synthesis scripts, and complete technical documentation along with 12 months of technical support.
The DF6805 is an advanced 8-bit MCU IP Core with highly sophisticated, on-chip peripheral capabilities. The DF6805 soft core is binary-compatible with the industry standard Motorola 68HC05 8-bit microcontroller. It can achieve the performance of 45 – 100 million instructions per second. The DF6805 has a FAST architecture that is 4.1 times faster compared to the original implementation. In the standard configuration, the core has major peripheral functions integrated on-chip. The DF6805 Microcontroller Core contains a full-duplex UART – Asynchronous Serial Communication Interface (SCI) and can be also equipped with the Synchronous Serial Peripheral Interface (SPI). The main 16-bit, free-running timer system has two input capture lines and two output-compare lines. Self-monitoring circuitry is included on-chip to protect against system errors. The Computer Operating Properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt if an illegal opcode is detected. Two software-controlled power-saving modes – WAIT and STOP are available to preserve additional power. These modes make the DF6805 IP Core especially attractive for automotive and battery-driven applications. The DF6805 is fully customizable – delivered in the exact configuration to meet your requirements. There’s no need to pay extra for unused features and wasted silicon. It includes a fully automated test bench with a complete set of tests, allowing easy package validation at each stage of the SoC design flow. Each DCD’s DF68XX Core has built-in support for a proprietary Hardware Debug System called DoCD™. It is a real-time hardware debugger that provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides a non-intrusive debugging of running applications. It can halt, run, step into or skip an instruction, and read/write any contents of the microcontroller, including all registers, and SFRs, including user-defined peripherals, data, and program memories. ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.
Digital Core Design presents DF6808, an advanced 8-bit MCU IP Core, crafted as a fast, binary-compatible evolution of the Motorola 68HC08 microcontroller. This IP core is renowned for its robust architecture, achieving up to 100 MIPS and supporting various communications interfaces, including a full-duplex UART and SPI. It features ample on-chip peripheral functionality, a 16-bit timer system, and mechanisms for ensuring operational integrity, including watchdog timers and self-monitoring circuitry. The DF6808 supports configurations for both Harvard and Von Neumann architectures, with customizable implementations that consider customer-specific requirements, thus eliminating unnecessary features and costs. Moreover, comprehensive debugging is facilitated with the DoCD™ hardware debugger. This core is a prime choice for automotive and resource-conscious battery applications, packed with power-saving modes. It offers compatibility with all major foundry technologies, ensuring seamless integration into FPGA and ASIC projects.
The DF6811E is an advanced 8-bit MCU IP Core with highly sophisticated, on-chip peripheral capabilities. The IP Core is binary-compatible with the industry-standard Motorola 68HC11 8-bit microcontroller. It has an improved FAST architecture, which is approximately 4 times faster compared to the original implementation. In the standard configuration, the core has major peripheral functions integrated on-chip. It can be provided in configurations that match the 68HC11A, 68HC11D, and 68HC11E specifications. There are two serial interfaces: an asynchronous serial communications interface (SCI) and a separate synchronous serial peripheral interface (SPI). The main 16-bit, free-running timer system has three input capture lines, five output-compare lines, and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods. Self-monitoring circuitry is included on-chip to protect against system errors. The Computer Operating Properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt if an illegal opcode is detected. Two software-controlled power-saving modes – WAIT and STOP are available to save additional power. These modes make the DF6811 IP Core especially attractive for automotive and battery-driven applications. The DF6811E Microcontroller Core can be equipped with an ADC Controller, allowing the use of an external ADC Controller with standard ADC software. The ADC Controller makes external ADCs visible as internal ADCs in original 68HC11E Microcontrollers. The DF6811E is fully customizable – delivered in the exact configuration to meet your requirements. There is no need to pay extra for unused features and wasted silicon. The DF6811E comes with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of SoC design flow. Each DCD’s DF68XX Core has built-in support for a proprietary Hardware Debug System called DoCD™ – a real-time hardware debugger providing the debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ allows non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, and read/write any contents of the microcontroller, including all registers, and SFRs, including user-defined peripherals, data, and program memories. DCD’s IP Cores are technology agnostic, ensuring 100% compatibility with all FPGA and ASIC vendors. The DF6811E’s innovative design and compatibility make it a leading choice in microcontroller solutions.
The DF6811F is an advanced 8-bit MCU IP Core with highly sophisticated, on-chip peripheral capabilities. The core is binary-compatible with the industry standard Motorola 68HC11F 8-bit microcontroller. It has an improved FAST architecture which is approximately 4 times faster compared to the original implementation. In the standard configuration, the core has major peripheral functions integrated on-chip. The Core can be provided in configurations that match the: 68HC11F. There are two serial interfaces: an asynchronous serial communications interface (SCI) and a separate synchronous serial peripheral interface (SPI). The main, 16-bit, free-running timer system has three input capture lines, five output-compare lines, and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events and measure external periods. Self-monitoring circuitry is included on-chip to protect against system errors. The Computer Operating Properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt if an illegal opcode is detected. Two software-controlled power-saving modes – WAIT and STOP are available to save additional power. These modes make the DF6811F IP Core especially attractive for automotive and battery-driven applications. The DF6811F Microcontroller Core can be equipped with an ADC Controller, allowing the use of an external ADC Controller with standard ADC software. The ADC Controller makes external ADCs visible as internal ADCs in original 68HC11F Microcontrollers. The DF6811F is fully customizable – it is delivered in the exact configuration to meet your requirements. There is no need to pay extra for unused features and wasted silicon. It comes with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of SoC design flow. Each DCD’s DF68XX Core has built-in support for a proprietary Hardware Debug System called DoCD™. It is a real-time hardware debugger that provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, and read/write any contents of the microcontroller, including all registers, and SFRs, including user-defined peripherals, data, and program memories.
The DF6811K is an advanced 8-bit MCU IP Core with highly sophisticated, on-chip peripheral capabilities. DCD’s soft core is binary-compatible with industry-standard Motorola 68HC11K 8-bit microcontroller. It has an improved FAST architecture – approximately 4 times faster compared to the original implementation. In the standard configuration, the core has major peripheral functions integrated on-chip. The Core can be provided in configurations that match the following microcontrollers: MC68HC11K0, MC68HC11K1, MC68HC11K4, MC68HC711K4, MC68HC11KS2, MC68HC711KS2. There are two serial interfaces: an asynchronous serial communications interface (SCI) and a separate synchronous serial peripheral interface (SPI). The main 16-bit, free-running timer system has three input capture lines, five output-compare lines, and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods. Self-monitoring circuitry is included on-chip to protect against system errors. The Computer Operating Properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt if an illegal opcode is detected. Two software-controlled power-saving modes – WAIT and STOP – are available to save additional power. These modes make the DF6811K IP Core especially attractive for automotive and battery-driven applications. The DF6811K Microcontroller Core can be equipped with the ADC Controller, allowing the use of an external ADC Controller with standard ADC software. The ADC Controller makes external ADCs visible as internal ADCs in original 68HC11K Microcontrollers. The core is fully customizable – delivered in the exact configuration to meet users’ requirements. There is no need to pay extra for unused features and wasted silicon. It includes a fully automated test bench with a complete set of tests, allowing easy package validation at each stage of the SoC design flow. Each DCD’s DF68XX Core has built-in support for a proprietary Hardware Debug System called DoCD™ – a real-time hardware debugger that provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of the running application. It can halt, run, step into or skip an instruction, and read/write any contents of the microcontroller, including all registers, and SFRs, including user-defined peripherals, data, and program memories. ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.
The DFPIC1655X is a low-cost, high-performance, 8-bit, fully static soft IP Core, intended to operate with fast memory. The core is designed with a special concern about low power consumption in combination with high performance. The DFPIC1655X is software compatible with industry-standard PIC 16XXX Microcontrollers. It has a modified RISC architecture (2 times faster than the original implementation). It has enhanced core features, a configurable hardware stack, and multiple internal and external interrupt sources. Separate instruction and data buses allow a 14-bit wide instruction word with a separate 8-bit wide data. Built-in power save mode and small area use in programmable devices, make this IP core perfect for applications with space and power consumption limitations. The DFPIC1655X is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of the SoC design flow.
The DFPIC165X is a low-cost, high-performance, 8-bit, fully static soft IP Core, dedicated to operating with fast memory (typically on-chip). The core is designed with a special concern for low power consumption. It is software compatible with PIC16C54, PIC16C55, PIC16C56, PIC16C57, and PIC16C58 industry standards, containing modified RISC architecture that is 2 times faster than the original implementation. It features separate instruction and data buses allowing a 12-bit wide instruction word, with a separate 8-bit wide data path. The DFPIC165X typically achieves a 2:1 code compression and an 8:1 speed improvement over other 8-bit microcontrollers in its class. The Core has 24 I/O lines, an 8-bit timer/counter with an 8-bit programmable Prescaler, and power-down SLEEP mode. It's ideal for high-speed automotive, low-power remote transmitters/receivers, and telecom processors. It supports a proprietary Hardware Debug System called DoCD™ for real-time, non-intrusive debugging.
The DFPIC166X is a low-cost, high-performance, 8-bit, fully static soft IP Core. The core was designed with a special concern about low power consumption, assuring the best power use, price, and performance combination available on the IP core market. The DFPIC166X softcore is the software compatible with industry-standard PIC 16XXX Microcontrollers. It implements an enhanced Harvard architecture (separate instruction and data memories) with independent address and data buses. 14-bit program memory and 8-bit dual port data memory allow instruction fetch and data operations to occur simultaneously. The advantage of this architecture is that the instruction fetch and memory transfers can be overlapped by a multi-stage pipeline so that the next instruction can be fetched from program memory while the current instruction is executed with data from the data memory. The DFPIC166X architecture is 2 times faster compared to the standard architecture. The DFPIC166X Microcontroller fits perfectly in applications ranging from high-speed automotive and appliance motor control, to low-power, remote transmitters/receivers, pointing devices, and telecom processors. Built-in power save mode makes this IP core perfect for applications where the power consumption aspect is critical. The DFPIC166X is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of the SoC design flow. Each DCD’s PIC Core has built-in support for a Hardware Debug System called DoCD™. It is a real-time hardware debugger that provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, read/write any contents of the microcontroller, including all registers, SFRs, user’s defined peripherals, data and program memories. ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.
The DP8051 is an ultra-high performance, speed-optimized softcore, of a single-chip 8-bit embedded controller, intended to operate with fast (typically on-chip) and slow (off-chip) memories. The core was designed with a special concern about the performance to power-consumption ratio. This ratio is extended by the PMU – an advanced power management unit. The DP8051 softcore is 100% binary-compatible with the industry standard 8051 8-bit microcontrollers. There are two configurations of the DP8051: Harvard, where internal data and program buses are separated and von Neumann, with a common program and external data bus. The DP8051 has a Pipelined RISC architecture and executes 120-300 million instructions per second. Dhrystone 2.1 benchmark program runs from 11.46 to 15.55 times faster than the original 80C51 at the same frequency. The same C compiler was used for benchmarking of the core vs 80C51, with the same settings. This performance can also be exploited to great advantage in low-power applications, where the core can be clocked over ten times slower than the original implementation, without performance depletion. The DP8051 is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation, at each stage of the SoC design flow. Each of DCD’s 8051 Cores has built-in support for the Hardware Debug System called DoCD™. It is a real-time hardware debugger, which provides debugging capability of the whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, and read/write any contents of the microcontroller, including all registers, internal and external program memories, and all SFRs, including user-defined peripherals. ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.
DP8051CPU is an ultra high performance 8-bit soft core microcontroller designed by DCD-SEMI to be highly efficient in terms of speed and power consumption. With a pipelined RISC architecture, it can perform operations remarkably faster than the traditional 80C51, with its performance metrics standing up to 15.55 times its predecessor when benchmarked using Dhrystone 2.1. The architecture supports both Harvard and von Neumann configurations, increasing the flexibility for memory access and inclusion. The microcontroller is equipped with an advanced Power Management Unit, allowing it to maintain its high performance capabilities while optimizing power consumption. Targeted for carrying out operations with both fast on-chip memory and slower off-chip alternatives, it can process up to 300 million instructions per second while managing substantial code and data spaces efficiently. Furthermore, it is 100% compatible with the industry-standard 8051 microcontrollers in terms of binary operation, making it highly suitable for integration in existing systems. It boasts of supporting a wide variety of interfaces like USB, Ethernet, I2C, SPI, UART, and many others, which adds to the scope of applications, especially in portable and power-conscious devices. The microcontroller supports a comprehensive hardware debugging system (DoCD™), uniquely proposed to allow non-intrusive debugging of an operational application, offering a robust development and testing phase. With real-time capability and providing insights at various operational stages, it ensures that users can have a contained yet exhaustive overview of their designs. DCD ensures a technology-agnostic design, meaning that this IP core ensures compatibility across all prominent FPGA and ASIC vendors, providing flexibility and convenience for a wide array of users. The DP8051CPU is delivered with a complete test bench and a series of validation sets, ensuring a smooth integration within any workflow.
The DP8051XP is an ultra-high performance , speed- optimized softcore, of a single-chip, 8-bit embedded controller, intended to operate with fast (typically on-chip) and slow (off-chip) memories. The core was designed with a special concern about the performance to power-consumption ratio. This ratio is extended by the PMU – an advanced power management unit. The DP8051XP softcore is 100% binary-compatible with an industry-standard 8051 8-bit microcontroller. There are two configurations of the DP8051XP: Harvard, where internal data and program buses are separated, and von Neumann, with common program and external data bus The DP8051XP has a Pipelined RISC architecture and executes 120-300 million instructions per second. Dhrystone 2.1 benchmark program runs from 11.46 to 15.55 times faster than the original 80C51 at the same frequency. The same C compiler was used for benchmarking of the core vs 80C51 with the same settings. This performance can be also exploited to great advantage in low- power applications, where the core can be clocked over ten times slower than the original implementation, without performance depletion. The DP8051XP is delivered with a fully automated test bench and a complete set of tests , allowing easy package validation at each stage of the SoC design flow. Each of DCD’s 8051 Cores has built-in support for a proprietary Hardware Debug System called DoCD™. It is a real-time hardware debugger, which provides debugging capability of a whole System-on-Chip (SoC). Unlike other on- chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, and read/write any contents of the microcontroller, including all registers, internal and external program memories, and all SFRs, including user-defined peripherals. ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.
The DP80C51 is an ultra-high performance, speed-optimized soft core of a single-chip 8-bit embedded controller, intended to operate with fast (typically on-chip) and slow (off-chip) memories. The core was designed with a special concern for the performance to power-consumption ratio. This ratio is extended by an advanced power management unit (PMU). The DP80C51 softcore is 100% binary and pins compatible with the industry standard 8051 8- bit microcontrollers. There are two configurations of the DP80C51: Harvard, where external data and program buses are separated, and von Neumann, with common program and external data bus. The DP80C51 has a Pipelined RISC architecture (up to 10 times faster compared to the standard architecture) and executes 85-200 million instructions per second. This performance can be also exploited to great advantage in low-power applications, where the core can be clocked over ten times slower than the original implementation, without performance depletion. The DP80C51 is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of SoC design flow. Each of DCD’s 8051 Cores has built-in support for the proprietary Hardware Debug System, called DoCD™. It is a real-time hardware debugger, which provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of running applications.
The DQ80251 is a revolutionary Quad-Pipelined ultra-high performance, speed optimized soft core of a 16-bit/32-bit embedded microcontroller. The core is fully configurable, allowing easy selection of features and peripherals to create a dedicated system. Designed with consideration for performance to power consumption ratio, it includes an advanced power management unit (PMU). The DQ80251 leverages decades of expertise with the 8051 architecture and is 100% binary-compatible with industry-standard 16-bit 80C251 and 8-bit 80C51 microcontrollers. Operating in BINARY and SOURCE modes, it offers significantly faster performance compared to the original architectures. It includes a built-in configurable DoCD-JTAG on-chip debugger and is technology agnostic, ensuring compatibility with all FPGA and ASIC vendors. The core integrates seamlessly with existing systems, providing extensive flexibility and capability in creating custom solutions.
The DQ8051XP is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded microcontroller. It is designed to operate efficiently with both on-chip and off-chip memories, ensuring a high performance-to-power consumption ratio. It is fully customizable and binary compatible with industry standard 8051 microcontrollers. The DQ8051XP achieves up to 29.01 times the performance of the original 80C51 at the same frequency, making it ideal for both high performance and low power applications. It comes with a power management unit, JTAG debugger support, and is versatile enough to handle multiple interfaces including USB, Ethernet, I2C, SPI, UART, CAN, LIN, and more. The core is delivered with comprehensive test environments and support, allowing for seamless integration into FPGA and ASIC designs.
The DRPIC1655X is a low-cost , high-performance , 8-bit, fully static soft IP Core, intended to operate with fast, dual-ported memory. The core has been designed with a special concern about low power consumption, assuring the best power use, price, and performance combination available on the IP core market. DCD’s IP Core is software- compatible with industry-standard PIC 16XXX Microcontrollers. It implements an enhanced Harvard architecture (separate instruction and data memories) with independent address and data buses. The 14-bit program memory and 8-bit dual port data memory allow instruction fetch and data operations to occur simultaneously. The advantage of this architecture is that instruction fetch and memory transfers can be overlapped by a multi-stage pipeline so that the next instruction can be fetched from program memory, while the current instruction is executed with data from the data memory. The DRPIC1655X architecture is 4 times faster compared to the standard architecture . Most instructions are executed within 1 system clock period, except the instructions which operate directly on a PC (GOTO, CALL, RETURN) program counter. This situation requires the pipeline to be cleared and subsequently refilled. This operation takes an additional one clock cycle. The DRPIC1655X Microcontroller fits perfectly in applications ranging from high-speed automotive and appliance motor control, to low-power remote transmitters/receivers, pointing devices, and telecom processors. Built-in power save mode makes this IP core perfect for applications where the power consumption aspect is crucial. The DRPIC165X is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of the SoC design flow. Each of DCD’s PIC Cores has built-in support for a proprietary Hardware Debug System called DoCD™. It is a real-time hardware debugger that provides debugging capability of a whole System-on-Chip (SoC). Unlike other on- chip debuggers, the DoCD™ allows non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, and read/write any contents of the microcontroller, including all registers, and SFRs, including user-defined peripherals, data, and program memories.
The DRPIC166X is a low-cost, high-performance, 8-bit, fully static soft IP Core, intended to operate with fast (typically on-chip) dual-ported memory. The core was designed with special concern about low power consumption, assuring the best power use, price, and performance combination available on the market. The DRPIC166X softcore is software-compatible with industry-standard PIC 16XXX Microcontrollers. It implements an enhanced Harvard architecture (separate instruction and data memories) with independent address and data buses. The 14-bit program memory and 8-bit dual port data memory allow instruction fetch and data operations to occur simultaneously. The DRPIC166X architecture is 4 times faster compared to the standard architecture. It fits perfectly in applications ranging from high-speed automotive and appliance motor control to low-power, remote transmitters/receivers, pointing devices, and telecom processors. The DRPIC166X is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of the SoC design flow. It includes the DoCD™ debug unit, which is a real-time hardware debugger providing non-intrusive debugging capabilities.
The DT8051 is a tiny soft core of a single-chip 8-bit embedded microcontroller, based on the world's fastest and most popular DP8051 core. It is 100% binary-compatible with the industry standard 8051 8-bit microcontrollers, with a very low gate count architecture of 6,650 ASIC gates including the DoCD on-chip debugger. The DT8051 runs Dhrystone 2.1 benchmark program exactly 8.1 times faster than the original 80C51 at the same frequency, using the same C compiler and settings. It includes a 2-wire DoCD on-chip debugger (TTAG™), eight external interrupt sources, an advanced Power Management Unit, full duplex UART, and more. It is suitable for low power battery-operated devices, mixed signal systems, and area optimized FPGA/ASIC designs.
**DRV64IMZicsr – 64-bit RISC-V Performance. Designed for Demanding Innovation.** The DRV64IMZicsr is a powerful and versatile 64-bit RISC-V CPU core, built to meet the performance and safety needs of next-generation embedded systems. Featuring the M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug extensions, this core is engineered to scale—from edge computing to mission-critical applications. As part of the DRVX Core Family, the DRV64IMZicsr embodies DCD’s philosophy of combining open-standard freedom with customizable IP excellence—making it a smart and future-proof alternative to legacy architectures. ✅ Why Choose RISC-V? * No license fees – open-source instruction set means reduced TCO * Unmatched flexibility – tailor the architecture to your specific needs * A global, thriving ecosystem – support from toolchains, OSes, and hardware vendors * Security & longevity – open and verifiable architecture ensures trust and sustainability 🚀 DRV64IMZicsr – Core Advantages: * 64-bit RISC-V ISA with M, Zicsr, and Debug support * Five-stage pipeline, Harvard architecture, and efficient branch prediction * Configurable memory size and allocation for program and data spaces Performance optimized: * **Up to 2.38 CoreMark/MHz** * **Up to 1.17 DMIPS/MHz** * Compact footprint starting from just 17.6k gates * Interface options: AXI, AHB, or native * Compatible with Classical CAN, CAN FD, and CAN XL through additional IPs 🛡️ Safety, Compatibility & Flexibility Built In: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Technology-agnostic – works seamlessly across all FPGA and ASIC vendors * Expandable with DCD’s IP portfolio: DMA, SPI, UART, I²C, CAN, PWM, and more 🔍 Robust Feature Set for Real Applications: * Full 64-bit processing – ideal for performance-intensive, memory-heavy tasks * M extension enables high-speed multiplication/division via dedicated hardware unit * Zicsr extension gives full access to Control and Status Registers, enabling: * Interrupts and exception handling (per RISC-V Privileged Spec) * Performance counters and timers * JTAG-compatible debug interface – compliant with RISC-V Debug Spec (0.13.2 & 1.0.0) 🧪 Ready for Development & Integration: * Comes with a fully automated testbench * Includes a comprehensive suite of validation tests for smooth SoC integration * Supported by industry-standard tools, ensuring a hassle-free dev experience Whether you’re designing for automotive safety, industrial control, IoT gateways, or AI-enabled edge devices, the DRV64IMZicsr gives you the performance, flexibility, and future-readiness of RISC-V—without compromise. 💡 Build smarter, safer systems—on your terms. 📩 Contact us today at info@dcd.pl to start your next RISC-V-powered project.
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