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Eliyan's NuLink Die-to-Die PHY for standard packaging is a technological innovation designed to enhance chiplet interconnectivity within conventional package forms. Tailored to seamlessly integrate with both silicon bridges and organic package substrates, this product eliminates the need for advanced packaging solutions while matching their performance characteristics. By achieving the same remarkable levels of data transfer efficiency and power optimization typically associated with advanced methods, NuLink technology stands out as a cost-effective solution for multi-die integration. Targeted for ASIC designs, the NuLink Die-to-Die PHY is capable of supporting a wide array of industry standards including UCIe and BoW. Its design enables the connection of chiplets in standard packaging without requiring large silicon interposers, ensuring both significant performance gains and cost savings. This flexibility makes it particularly appealing for systems that require mixing and matching of chiplets of varying dimensions. In practical applications, Eliyan’s solution facilitates increased placement flexibility and supports configurations that demand physical separation of components, such as those between hot ASICs and heat-sensitive dies. By leveraging a standard packaging approach, this PHY product provides substantial improvements in thermal management, cost efficiency, and production timelines compared to traditional methods.
Eliyan's NuLink Die-to-Memory PHY technology stands as a testament to the company's innovative approach toward enhancing semiconductor performance without resorting to advanced packaging. This IP solution offers low-power, high-performance connectivity capabilities for die-to-memory interconnects, utilizing the same foundational NuLink technology adapted for unique applications. Unlike traditional unidirectional designs, this PHY provides a more fluid data transfer, supporting a diverse range of industry standards while maintaining efficiency and adaptability. The NuLink Die-to-Memory PHY product allows integrations on both standard and advanced packaging, delivering exceptional performance metrics. In contrast to established methods that often necessitate complex silicon interposers, Eliyan’s solution is able to provide equivalent, if not superior, results using standard packaging techniques. Its structure is geared towards minimizing power consumption and maximizing data throughput, thus enabling the realization of more powerful and efficient semiconductors. This technology is particularly beneficial for applications requiring dynamic interfacing between dies and memory, making it viable for a multitude of cutting-edge electronic devices. By offering scalable and effective solutions, Eliyan facilitates advancements in both traditional memory coupling and emerging semiconductor technologies.
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