Is this your business? Claim it to manage your IP and profile
Optimized for Intel and AMD FPGAs, the Stream Buffer Controller from Enclustra facilitates efficient data transfer by bridging streams to memory-mapped DMA. This versatile IP core supports up to 16 independent streams, offering a virtual FIFO capability up to 4GB of buffer memory. It utilizes AMBA AXI4-Stream interfaces, enhancing data throughput and flexibility in various data-intensive applications. The core is highly configurable, allowing adjustments in buffer size and addressing to meet specific project needs. Operating modes for each channel include FIFO, write, read, and ROM, providing tailored memory access solutions. This configuration is managed through a memory-mapped slave interface, making it adaptable for use with an embedded CPU or a dedicated stream configuration controller. With support for multiple operational modes, data width conversions, and a unified bus interface, the Stream Buffer Controller is ideal for complex data handling applications like image processing and embedded systems. Its stand-alone capability makes it particularly attractive for projects aiming to minimize additional processing overhead, with a clear layout for straightforward integration into larger system designs.
The Universal DSP Library by Enclustra delivers streamlined solutions for digital signal processing within the AMD Vivado ML Design Suite. Providing a comprehensive library of DSP components like FIR and CIC filters, mixers, and CORDIC function approximations, the library enables developers to rapidly create signal processing chains. This is achieved through both raw VHDL source and Vivado IPI blocks, simplifying integration and significantly reducing development time. The library supports efficient bit-true software models in Python, allowing thorough evaluation of processing chains prior to FPGA implementation. This capability not only improves the development process but also provides a clear path from software simulation to hardware implementation. The DSP components are fully documented, with reference designs to guide users in combining various blocks to form complex DSP systems. Targeted at numerous applications such as software-defined radio and digital signal processing, the library addresses common DSP needs, freeing developers to concentrate on project-specific innovations. Furthermore, it supports multiple data channels and works with both continuous wave and pulse processing, utilizing the AXI4-Stream protocol for a standard interface structure.
Enclustra's Universal Drive Controller is a sophisticated IP core that manages motor control for DC, brushless, and stepper motors with precision. It's a comprehensive solution that incorporates position control and trajectory planning, eliminating the need for additional drive controller chips. This IP core helps save both precious PCB real estate and costs, while significantly speeding up the time-to-market for new applications. The core can control up to eight motors, handling all control loops autonomously, which reduces CPU demand. This autonomous operation ensures robust performance with minimal system resources, making it ideal for industries requiring precise motor control, such as robotics and automation. It integrates perfectly with industry-standard AXI-4 interfaces, offering a vendor-independent implementation with high customizability. The controller supports velocity and acceleration feeds for enhanced performance, and features microstepping capabilities for fine control of stepper motors. Additional functionalities include current, voltage, and temperature supervision, ensuring reliable and efficient motor operation under varying conditions.
Enclustra's UDP/IP Ethernet IP core is designed to simplify Ethernet communication for FPGA-based systems using the UDP protocol. Optimally implemented for AMD and Intel FPGA architectures, the core offers a straightforward interface to user logic, handling full UDP, IPv4, and Ethernet layer processing with ease. It supports a 1 Gbit/sec wire speed thanks to its efficient architecture and is compatible with common media independent interfaces. The core's configurability includes multiple UDP ports with distinct receive and transmit interfaces, as well as header pass-through modes that allow customization of header fields embedded in data streams. This IP core not only facilitates seamless communication between FPGA subsystems but does so with minimal resource usage and overhead, ideal for high-speed data exchange in test and measurement applications. Furthermore, it incorporates automatic ARP response generation and provides options for filtering destination UDP ports, IP addresses, and MAC addresses. These features ensure robust, reliable, and secure data exchanges across complex networks, making it highly suitable for environments where efficient and high-speed communication is critical.
Join the world's most advanced semiconductor IP marketplace!
It's free, and you'll get all the tools you need to evaluate IP, download trial versions and datasheets, and manage your evaluation workflow!
To evaluate IP you need to be logged into a buyer profile. Select a profile below, or create a new buyer profile for your company.
