Is this your business? Claim it to manage your IP and profile
The AES Key Wrap Core developed by IP Cores, Inc. implements the NIST-approved AES Key Wrap specification, ensuring secure key exchange and management. Utilizing both 128-bit and 256-bit AES keys for wrapping and unwrapping operations, this core fortifies the security infrastructure for communication and encryption-based applications. This IP core excels in scenarios requiring compact size without compromising security, starting from less than 8,000 gates and featuring a fully self-contained design that excludes the need for external memory. This, combined with its flow-through architecture, enhances its simplicity in integration and operation. Available in source code and netlist forms, the core also supports both encryption and decryption-only variants, further offering flexibility to meet varied design needs. Applications include secure key management systems complying with strict security protocols.
The DES/3DES Ultra-Compact Data Encryption Standard core by IP Cores, Inc. offers a compact implementation of the DES and Triple DES encryption standards, ideal for applications where size and efficiency are crucial. Supporting 64-bit block sizes and accommodating one to three 56-bit keys, it provides robust data security compliant with NIST FIPS standards. Engineered for minimal resource footprint, this core requires only 3,000 ASIC gates, making it perfect for areas where space and cost-efficiency are necessary. The DES/3DES core supports various cipher modes including ECB, CBC, and CTR, enabling flexibility in secure communication implementations. The fully synchronous design available in both Verilog and netlist forms allows for seamless integration and offers high throughput up to 3 Gbps, customizable for different process technologies. Deliverables include test benches and self-checking vectors for streamlining deployment.
The True Random Number Generator (TRNG) core by IP Cores, Inc. is designed for generating true random numbers suitable for high-security applications. Passing stringent tests like the NIST SP800-22 and Diehard Suites, this core provides reliable randomness that is crucial in cryptographic systems. Compact and efficient, the TRNG core leverages an on-chip entropy source and a pseudo-random generator to produce high-entropy outputs. This makes it ideal for applications that require random number generation meeting exacting cryptographic standards, such as secure communication protocols and digital rights management systems. Available for both ASIC and FPGA implementations, the core provides flexibility in its deployment, ensuring it can be tailored to fit various system requirements. Deliverables include source code and comprehensive test plans, ensuring straightforward integration and deployment.
The SNOW 3G LTE Encryption Core from IP Cores, Inc. is a high-performance solution designed to produce keystreams compliant with 3GPP LTE algorithms (UEA2 and UIA2). Built to meet ETSI/SAGE specifications, this core processes 128-bit key inputs to generate 32-bit block keystreams. With a compact design, utilizing approximately 7,500 gates, the SNOW3G1 core ensures minimal footprint while maintaining superior performance, supporting throughputs up to 7.5 Gbps. Its fully synchronous design allows for straightforward integration into systems, enhancing mobile communication encryption efficiently. Ideal for secure mobile communications, particularly in 3GPP LTE networks, this core supports high-speed data encryption while ensuring compliance with industry standards. The core is available in Verilog form, complete with test vectors and synthesis scripts for accelerated implementation.
The Ultra-Compact Advanced Encryption Standard IP core from IP Cores, Inc. offers a highly efficient implementation of the AES algorithm, which is known for its robust security and versatility. This IP core processes data blocks using 128-bit keys, with optional support for 256-bit keys, facilitating both encryption and decryption operations in compliance with NIST's Advanced Encryption Standard. Designed to optimize for size, this core minimizes the gate count required, enabling cost-effective deployment in various ASIC and FPGA configurations. The AES core supports multiple modes of operation such as ECB, CBC, and CTR, making it versatile for numerous applications including secure communications, DRM, and more. The core's architecture is fully synchronous, providing a self-contained module that does not require external memory, thereby simplifying integration into larger systems. Deliverables include synthesizable Verilog or VHDL source code, making it adaptable to specific project needs.
IP Cores, Inc.'s Ultra-Compact Kasumi Cipher Core offers a highly efficient hardware implementation of the Kasumi cipher, meeting ETSI SAGE and 3GPP specifications. Tailored for secure mobile communications, this core excels in maintaining data integrity with 64-bit block processing. Characterized by its compact structure, the KSM1 core utilizes only 5,500 gates, supporting high throughput up to 3 Gbps, making it ideal for areas where space and power are limited. Designed for encryption-only applications, it fits perfectly into systems requiring compact and robust cryptographic processing. This core's design is fully synchronous and provides flexibility by supporting various cipher modes like ECB and CBC. Delivered in portable Verilog format, it allows ease of integration and supports verification with comprehensive test vectors.
The Combo GCM/CCM/EAX Core by IP Cores, Inc. integrates multiple encryption/authentication modes, bringing versatility and security to advanced encryption needs. This core supports GCM, CCM, CCM*, and EAX modes in compliance with AES standards, optimizing for both speed and security. Supporting operations at scalable throughput rates, from 0.8 to 12.8 bits per clock, it offers a robust encryption solution for applications such as IEEE 802.15.4 Zigbee and IPsec, ensuring data integrity and security across communication channels. Its fully synchronous design allows for seamless interfacing with microprocessor systems. Available in Verilog form, the core facilitates easy integration, accompanied by test benches and synthesis tools for a streamlined development process. It provides comprehensive support for secure data processing in high-demand environments requiring advanced encryption standards.
IP Cores, Inc.'s Cryptographically Secure Pseudo Random Number Generator is an advanced core compliant with NIST SP800-90 for generating secure random numbers crucial for cryptographic operations. Using the CTR_DRBG algorithm, it supports security strengths up to 256 bits and outputs 128-bit random data blocks. Characterized by its compact size, the PRNG1 core includes an AES core and features a flexible data interface ranging from 8 to 128 bits. This flexibility makes it suitable for a variety of security-centric applications such as secure communications, DRM, and financial transactions, where high levels of cryptographic security are paramount. Available in both Verilog and VHDL formats, the core's fully synchronous design enables ease of integration while maintaining high performance standards. Deliverables include synthesizable source code and comprehensive test benches, ensuring reliable deployment in target systems.
SHA1 and SHA2 Cryptographic Hash Cores from IP Cores, Inc. offer robust solutions for generating secure hash functions critical for ensuring data integrity and authenticity. Supporting SHA-1, SHA-256, and SHA-512 standards, these cores are optimized for high-speed operations suited for a range of security protocols. Designed for flow-through operations, these cores can be easily integrated into communication systems, providing parameterized data bus width flexibility to fit various application needs. They deliver high-performance hashing while maintaining small form factor designs that require minimal additional memory. Ideal for use in digital signature applications and security protocols such as TLS/SSL and IPSec, these cores ensure compliance with Federal Information Processing Standards, offering well-rounded cryptographic solutions that are fully Verilog-supported.
Join the world's most advanced semiconductor IP marketplace!
It's free, and you'll get all the tools you need to discover IP, meet vendors and manage your IP workflow!
To evaluate IP you need to be logged into a buyer profile. Select a profile below, or create a new buyer profile for your company.
