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The RV32EC_P2 Processor Core by IQonIC Works is a streamlined 2-stage pipeline RISC-V processor designed for low-power embedded applications running trusted firmware. This processor core supports ASIC and FPGA design flows and implements the RISC-V RV32E instruction set, complemented by optional standard extensions like integer multiplication and division. The core allows for specific instruction set extensions, such as for Digital Signal Processing (DSP) operations, enhancing its adaptability to various applications. Key features include a simple machine-mode architecture with direct physical memory access and the support for up to 20 extended interrupts. It has a clock-efficient 2-stage pipeline, optimized for speed with most instructions completing in a single cycle. For low-power operation, the design includes provisions for clock gating during idle states, making it ideal for energy-sensitive use cases. The processor interfaces with AHB-Lite or APB for extended memory and memory-mapped I/O. This core is highly configurable, adaptable for various embedded scenarios with support for RISC-V Privileged Architecture, and offers comprehensive memory interfaces to fit different design needs. IQonIC Works provides extensive tooling and support, including a compatible GNU tool chain and Eclipse development environment, ensuring developers can leverage this processor's full potential.
The RV32IC_P5 is a 5-stage pipeline RISC-V processor core suited for medium-scale embedded applications requiring higher performance and cache capabilities. This core enhances system capability by providing features including 16-bit compressed instructions and options for standard extensions, such as support for machine-mode protected application execution. It comprises a robust architecture with machine, and user-mode functionalities, supporting up to 20 extended interrupts and optional user-mode extensions for handling exceptions. This design is aimed at enhancing multitasking and system performance, with an optional predictive branching system to reduce latency. With tight integration capabilities, it connects strategically to AHB-Lite interfaces and advanced memory mapped systems, offering support for virtual prototyping and extensive toolchain development environments, suitable for applications demanding rigorous performance enhancements within an embedded context.
The RISC-V Platform-Level Interrupt Controller (PLIC) IP provided by IQonIC Works is an essential component for managing interrupts across systems with many sources and targets. This IP is highly configurable, allowing designers to adjust the number of interrupt sources and targets to fit specific application needs while maintaining compatibility with the RISC-V PLIC specifications. This interrupt controller supports wide-ranging interrupt sensitivity options, synchronous or asynchronous signal configurations, and various edge or level sensitivities. The flexible architecture easily integrates into systems through an AHB-Lite interface, handling priority setting, enabling interrupts, and managing the complete lifecycle of interrupt requests. IQonIC Works PLIC IP is designed to accommodate both single and multi-processor environments, efficiently controlling and delegating interrupts across multiple operation contexts. The PLIC offers secure interrupt handling and allocation, ensuring reliable performance in both machine and user-mode contexts, essential for applications with stringent mission-critical performance requirements.
IQonIC Works offers the RISC-V Timer IP which encapsulates a suite of timers adherent to the RISC-V machine timer specifications, tailored for various embedded system applications. This component is crucial for timekeeping and managing operation cycles efficiently across a multitude of systems that range from simple clock-synchronous applications to complex low-power timed mechanisms. The IP is adaptable, providing variants for AHB or APB bus interfaces, allowing integration into different system architectures from simple to intricate infrastructure designs. Whether the requirement is for clock-domain crossing support or operating autonomously with a low-frequency clock, IQonIC Works provides a flexible solution catering to diverse power and operational needs. Developers can leverage these timers for precise time management necessary in sophisticated systems, with varied configurations to match the hardware architecture’s demanding requirements. Through its thoughtful design, RISC-V Timer IP promotes efficient resource utilization and sharpens the response times of time-sensitive applications.
IQonIC Works' USB-C/PD IP offers a comprehensive set of design solutions for integrating USB-C/PD functions into IC/ASIC environments. This IP is crafted to support varied applications from single to full dual role port configurations, and includes flexible design options for both hardware needs and firmware implementations to cater to diverse integration scenarios. The IP enables manufacturers to handle core functions whether through hardware-only solutions, firmware-enhanced implementations, or as a peripheral supplement to existing systems for shared CPU management. This adaptability allows developers to choose the integration model that best suits their product development cycle and technical requirements. Supported by detailed design documentation, robust development boards, and verification environments, IQonIC Works ensures that their USB-C/PD offerings facilitate seamless integration and device performance. These IP blocks offer versatile licensing options and are geared for expansive applicability across various industries seeking to harness the full potential of USB-C technology.
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