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The Network Protocol Accelerator Platform (NPAP) is designed to optimize network protocol processing using FPGA technology. Developed in collaboration with Fraunhofer Heinrich-Hertz-Institute, NPAP facilitates ultra-high-speed data communication over Ethernet connections ranging from 1G to 100G. The IP core offloads TCP/UDP/IP processing to programmable logic, significantly enhancing network throughput while reducing latency. NPAP is a flexible and customizable turnkey solution suitable for both FPGA and ASIC implementations, boasting an impressive feature set that includes multiple parallel TCP engines and a robust stream interface for data handling. This accelerator caters to environments requiring seamless and rapid data exchanges, such as smart network interface cards (SmartNICs), in-network compute acceleration, and video-over-IP setups. Supporting full TCP/UDP/IP protocol stacks implemented in HDL, the NPAP enables FPGAs to achieve line rates up to 70 Gbps, with even higher capabilities in ASIC form. Optional enhancements like DPDK stream interfaces and Corundum NIC integrations further broaden its application range, making it ideal for demanding tasks in test and measurement or automotive systems. MLE provides a remote evaluation system for NPAP, allowing for hands-on testing in a controlled setting, thus enabling clients to assess performance before implementation. The platform's implementation includes the use of Xilinx's Zynq UltraScale+ MPSoC, leveraging cutting-edge FPGA technology to bring these high-speed communication solutions to life.
The NVMe Streamer is a specialized IP core designed for high-speed data streaming using the NVMe storage protocol. Built to facilitate performance-driven applications, the NVMe Streamer fully integrates NVMe host capability into programmable logic, eliminating the need for CPU dependency in data transfer operations. This core supports PCIe connectivity and is compatible with Xilinx's FPGA families, utilizing their GTH and GTY transceivers to achieve fast and efficient storage interactions. Ideal for high-throughput environments, the NVMe Streamer caters to applications requiring immediate data capture and processing, such as automotive data logging and aerospace data acquisition. By completely managing NVMe protocols in programmable logic, it reduces computational overhead, freeing up CPU resources for other tasks. This integration allows for seamless streaming of data from NVMe SSDs to other system components or external storage devices. The NVMe Streamer offers enriched features including PCIe enumeration, queue management, and multi-lane PCIe support, making it highly adaptable to varied data-intensive infrastructures. With its footprint optimized for minimal resource use and excellent performance scaling, the NVMe Streamer underscores MLE's commitment to delivering robust IP solutions tailored for the modern data-centric world.
The Key-Value-Store Accelerator is designed to enhance data center storage capabilities through FPGA-based acceleration. This advanced IP core integrates seamlessly into high-performance computing environments, supporting key data flow applications such as object storage and in-memory compute. Built on a Xilinx Zynq UltraScale+ platform, the accelerator features networked storage nodes, allowing for concurrent processing at high data throughputs while maintaining low latency. By facilitating line-rate TCP/IP and Memcached processing within a flexible, programmable logic framework, the accelerator reduces overall server power consumption, supporting 10 to 100 GigE speeds. This makes it well-suited for modern data centers seeking to optimize transaction processing speeds and server efficiency. With a modular HDL and C/C++ framework, the solution offers extensive customization for various storage architectures, ensuring adaptability to shifting data demands. MLE offers technology support and design services for integrating the accelerator technology into client applications, providing an end-to-end solution that includes out-of-order memory controllers and interfaces for DRAM and SSD connectivity. The accelerator not only increases storage capability and efficiency but also strengthens the infrastructure's ability to handle data-intensive tasks effortlessly.
The Low Latency Ethernet MAC IP Core, developed in collaboration with Fraunhofer Heinrich-Hertz-Institute, supports high efficiency and speed for 10G and 25G Ethernet connections. It provides a platform-independent interface with low resource utilization that supports AXI4-Stream protocols on both client transmit and receive channels. The core's advanced design ensures latency as low as 19.2ns at 156.25MHz, enabling swift data processing suitable for contemporary FPGA-based systems. Designed to accommodate a range of Ethernet applications, the MAC IP offers full support for VLAN tagged frames, promiscuous mode, and efficient data handling through the Deficit Idle Count mechanism. It's highly customizable, allowing users to adjust frame length and tailor the core's resource demands to project requirements, which is especially beneficial for embedded system applications needing robust, reliable networking. MLE's MAC IP integrates seamlessly with broader networking architectures, offering both a flexible and efficient solution for diverse communication challenges. By focusing on low-latency performance, it ensures optimal throughput in data-heavy environments, making it ideal for storage, gaming, and media streaming sectors that require consistent high-speed Ethernet connections.
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