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The Hybrid Ultra-Low Latency (ULL) FPGA Framework from Orthogone combines the high performance of FPGA hardware with the flexibility of software components, designed specifically for high-frequency trading (HFT) and similar applications. This FPGA Framework provides a comprehensive set of IP cores and a versatile development environment tailored to prototyping and optimizing ultra-low latency systems. The Framework allows seamless task allocation between FPGA and software, achieving impressive latency reduction and high transaction throughput, making it indispensable for trading operations where speed is critical. This hybrid framework is built to scale efficiently with business growth and adapts to evolving market conditions, facilitating easy integration into existing infrastructures. Its robust security features and real-time data processing capabilities ensure reliability and safety in operation 24/7. The framework includes a complete suite of cores such as 10G Ethernet MAC, TCP/UDP offload engines, and a PCIe DMA controller, all supported by an extensive FPGA development environment that simplifies application creation and deployment. Tailored to support AMD Alveo and Ultrascale+ FPGA platforms, the ULL FPGA Framework ensures adaptability with upcoming technologies. Its holistic software framework, inclusive of API libraries and drivers, enhances development efficiency by providing required tools for high-frequency trade and data exchange applications with reduced effort and time.
Orthogone's ULL Ethernet MAC & PCS core is engineered for applications requiring exceptional speed and efficiency, such as in financial and networking industries. This core excels in low latency environments, supporting data transfer at 1, 10, 25, 40, and 100 Gbps rates. Its capabilities are enhanced with error correction options like Reed Solomon FEC, ensuring data integrity in high-speed transactions. This Ethernet MAC & PCS implementation is based on a flexible Verilog architecture. It offers frame-check sequence verifications and supports broad traffic types with its sophisticated design, which includes programmable VLAN detection and advanced statistics management. The choice of optional logic parameters allows customization to specific requirements, making it a robust choice for varied use cases. By utilizing industry-leading latency margins, the core maintains efficient operation and high data integrity, suitable for demanding environments where packet loss isn't an option. Its resource-efficient design is ideal for applications that demand the highest throughput and reliability within stringent speed constraints.
The Ultra-Low Latency Ethernet MAC (Media Access Control) and PCS (Physical Coding Sublayer) by Orthogone are optimized for high-frequency trading, high-performance computing, and networking functions that demand minimal latency. These Ethernet MAC and PCS cores are capable of handling data rates ranging from 1 to 100 Gbps, providing unmatched speed and reliability for applications where time-critical tasks are essential. The design incorporates advanced techniques that ensure exceptional performance with minimal gate count and resources, making it ideal for reducing time-to-market in financial and networking applications. This sophisticated Ethernet solution supports a wide range of features including frame-check sequence insertion, multiple data widths, and optional RS-FEC for error correction in high-speed data transfers. The implementation leverages a unified Verilog codebase, streamlined to include extensive support for Ethernet standards such as IEEE 802.3, ensuring compliance with high-speed requirements while providing a robust feature set. The MAC maintains wireline speeds without packet drops, even at full throughput with jumbo frames, thanks to its efficient handling of back-to-back or mixed-length traffic. Among its key advantages are programmable VLAN detection and an option for Reed Solomon FEC for higher reliability, addressing complexities in varied deployment scenarios.
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