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The Alcora V-by-One HS FMC daughter card by Parretto facilitates the integration of V-by-One HS interfaces into FPGA systems with ease. It provides 8 RX and 8 TX lanes, allowing for a total of 16 lanes when two cards are used, capable of supporting 4K resolutions at 120Hz, or 8K at 30Hz. Designed for versatility, Alcora comes in two configurations: 51-pin and 41-pin headers. Built for stability, it includes two clock generators to synthesize the transceiver reference clock and reduce jitter, optimizing digital video transmission over the high-speed interface. V-by-One HS technology, developed by THine Electronics, Inc., positions the Alcora card as a prime component for high-resolution video and flat panel display markets, bridging the gap between superior video outputs and a variety of digital displays.
Tentiva is Parretto's versatile Video FMC board designed to enhance video processing with a high degree of modularity. It boasts two modular PHY slots enabling seamless customization and expansion, supporting up to 20 Gbps data rates. These slots serve as a high-speed channel between the Tentiva board and connected PHY cards. Suitable for a range of applications, Tentiva supports multiple PHY cards including DPT14X for DisplayPort 1.4 transmission, and DP21RX for reception, among others. This high level of adaptability means it's a robust choice for flexible video processing setups. Engineered to integrate smoothly with FPGA development boards that feature FMC headers, Tentiva offers broad compatibility with different manufacturers' hardware. Its flexible architecture makes it ideal for a wide range of video applications, demanding both performance and adaptability.
The JPEG-LS Encoder by Parretto is a powerful implementation aimed at providing superior lossless image compression. Known for its efficient use of resources, this encoder only requires minimal system memory and operates with less than one line of latency. Focusing on high-quality image compression, the JPEG-LS outperforms traditional JPEG-2000 standards, supporting depths of 8 to 16 bits per image sample. It ensures rapid performance by encoding one pixel per clock cycle, facilitating swift integration into streaming data interfaces. Configurable for various image sizes, even reaching ultra-high definition levels, this encoder supports customizable output data word width. It can be flexibly employed to maintain image fidelity in a diverse range of applications, from medical imaging to security systems.
The DisplayPort 1.4 core solution by Parretto is engineered to cater to the evolving needs of digital video streaming. This IP core functions as both a source and sink, supporting link rates of 1.62, 2.7, 5.4, and 8.1 Gbps, inclusive of embedded DisplayPort rates. It is compatible with 1, 2, and 4 DP lanes and features native video along with AXI stream interfaces. The core is designed to facilitate efficient video transportation via Single Stream Transport (SST) and Multi Stream Transport (MST) modes, offering support for dual and quad pixels per clock and 8 & 10-bit video. Additionally, it seamlessly manages RGB and YUV colorspaces, and incorporates a secondary data packet interface for audio. Enhanced with a Video Toolbox (VTB), this IP core allows for video processing tasks such as timing and pattern generation as well as video clock recovery, simplifying integration with a thin host driver and API. The IP is supported on various FPGA platforms like AMD UltraScale+, Artix-7, Intel Cyclone 10 GX, and Arria 10 GX.
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