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The 802.11 LDPC core facilitates high-throughput decoding in wireless communication systems. It supports dynamic frame-by-frame configuration, allowing adaptations between throughput and error correction performance. The core boasts configurable decoding iterations, aligning with required throughput and error rate specifications, delivering seamless performance for robust wireless designs.
The LTE Lite offers a high-performance PHY layer for user equipment with compliance to CAT 0/1 standards. Supporting flexible channel bandwidths, it works seamlessly with standard RF tuners. The design features automated demodulation via a controlling state machine and includes frequency and timing correction, ensuring accuracy even in high-offset environments. Synthesizable in Verilog-2001, it's highly adaptable for various telecommunication needs.
The DVB-S2 LDPC Decoder is tailored for digital video broadcasting over satellite applications, providing a reliable solution for error correction. The decoder utilizes LDPC codes concatenated with BCH codes, ensuring Quasi Error Free operation close to the Shannon limit. It features a layered decoding process with configurable iterations and conforms to ETSI standards, making it an ideal choice for high-quality satellite transmission systems.
Bit Chains are crucial IP components for handling variable bitframe structures in communications protocols like DVB-T2 and LTE. They are equipped to handle different modulation techniques and bandwidth requirements, offering flexibility in transmission characteristics. By accommodating short and long frames and diverse modulation schemes, Bit Chains serve to enhance the flexibility and efficiency of digital communication systems.
Application Specific Instruction Set Processors (ASIPs) from Wasiela are designed as special-purpose programmable hardware accelerators. These processors offer a customizable instruction set that aligns with specific application needs, optimally balancing performance with power efficiency. Suitable for diverse applications, ASIPs enable targeted functionality enhancements with minimal power consumption, delivering precise, reliable processing capability tailored to complex computational tasks.
Wasiela's Diversity MIMO Decoder line includes various configurations to optimize multiple input, multiple output (MIMO) processing. Offering features like the Fixed Depth K-Best Decoder, they support multiple synchronized data streams and different QAM types. These decoders enhance MIMO processing by achieving near Maximum Likelihood BER performance in different use-case scenarios.
Designed for digital signal processing, Wasiela's DSP Cores utilize advanced algorithms like the FFT, tailored for frequency domain transformations essential in telecommunication applications like LTE and DVBT2. These cores feature fully pipelined, parameterized architectures supporting highly efficient decimation and processing capabilities, emphasizing a balance between configurability and computational power.
Wasiela's En/Decryption solution provides a high-performance AES core capable of both encryption and decryption. Supporting various key lengths, it is designed to adapt to a wide range of input patterns. This core offers robust security features ideal for safeguarding digital communications and data integrity across networked and standalone environments.
Wasiela's PHY Tranceivers offer advanced modulation and demodulation capabilities, supporting standards like WiMAX and ZigBee. Integrating with RF tuners and other peripherals, these transceivers facilitate seamless digital communication across various frequencies. Their architectural design emphasizes precision in synchronization and timing, essential for effective connectivity in complex systems.
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