All IPs > Wireline Communication > Ethernet
The wireline communication category of Ethernet semiconductor IPs is pivotal in the development of modern high-speed data transfer technologies. Ethernet technology, a mainstay in networking, facilitates the connection of computers to local networks (LANs) and wide-area networks (WANs). This category focuses on semiconductor IPs that implement Ethernet protocols, enabling manufacturers to integrate high-performance networking capabilities into their electronic devices efficiently and cost-effectively.
Ethernet semiconductor IPs are crucial for designing networking chips used in a variety of enterprise, consumer, and industrial applications. These IPs provide the foundational building blocks for implementing Ethernet standards from legacy 10/100 Mbps to the latest Multi-Gigabit Ethernet, including 1G, 10G, 25G, and beyond. Enhanced with features like Energy Efficient Ethernet (EEE) and advanced security mechanisms, these semiconductor IPs ensure optimized performance and reliability essential for today’s data-intensive applications.
The products in this category include a diverse range of Ethernet MAC(medium access control) cores, PHY(physical layer) cores, and network interface controllers, among others. These components work together to manage data packet transmission over Ethernet networks, ensuring seamless communication between connected devices. Designers leverage these Ethernet IPs to create routers, switches, servers, and Internet of Things (IoT) devices that require sophisticated data handling capabilities.
By integrating Ethernet semiconductor IPs, developers and OEMs can achieve faster time-to-market while reducing design risk and cost. These IPs are pre-verified, ensuring compliance with the current Ethernet standards, which accelerates the development cycle for networking equipment. Consequently, Ethernet semiconductor IPs are indispensable for any entity aiming to innovate within the competitive landscape of wireline communication technologies.
The Metis AIPU PCIe AI Accelerator Card is engineered for developers demanding superior AI performance. With its quad-core Metis AIPU, this card delivers up to 214 TOPS, tackling challenging vision applications with unmatched efficiency. The PCIe card is designed with user-friendly integration in mind, featuring the Voyager SDK software stack that accelerates application deployment. Offering impressive processing speeds, the card supports up to 3,200 FPS for ResNet-50 models, providing a competitive edge for demanding AI tasks. Its design ensures it meets the needs of a wide array of AI applications, allowing for scalability and adaptability in various use cases.
The 1G to 224G SerDes is a versatile serializer/deserializer technology designed to facilitate high-speed data transfers across various interface standards. It caters to stringent speed requirements by supporting a wide range of data rates and signaling schemes, allowing efficient integration into comprehensive communication systems. This SerDes technology excels in delivering reliable, low-latency connections, making it ideal for hyperscale data centers, AI, and 5G networking where fast, efficient data processing is essential. The broad compatibility with numerous industry protocols also ensures seamless interoperability with existing systems. Adapted for scalability, the 1G to 224G SerDes provides design flexibility, encouraging implementation across a variety of demanding environments. Its sophisticated architecture promotes energy efficiency and robust performance, crucial for addressing the ever-growing connectivity demands of modern technology infrastructures.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
Ethernet MAC 10M/100M/1G/2.5G IP is a solution that enables the host to communicate data using the IEEE 802.3 standard for 10M, 100M, 1G, 2.5G speeds and is suited for use in networking equipment such as switches and routers. The Client-side interface for the IP is AXI-S and the Ethernet MAC IP comes with GMII, RGMII or MII interfaces on the PHY side. The Ethernet MAC 10M/100M/1G/2.5G IP features a compact and low latency solution, it is highly configurable and can optionally include IEEE 1588 Timestamping Unit (TSU). The Silicon agnostic Ethernet MAC IP, suitable for ASICs and FPGAs, is prepared for easy integration with Ethernet PCS 10M/ 100M/1G/2.5G IP from Comcores.
The ARINC 818 Product Suite by Great River Technology provides a comprehensive solution for high-performance digital video transmission in avionics applications. It supports the implementation, qualification, testing, and simulation of ARINC 818 products. This suite allows developers to access essential ARINC 818 tools and resources. It ensures optimal performance and reliability in mission-critical equipment by offering both hardware and software components tailored for the ARINC 818 standard. With its focus on high-speed data transfer and signal integrity, the ARINC 818 Product Suite is ideal for applications requiring lossless video transmission and real-time data handling in challenging conditions.
TTTech's Time-Triggered Ethernet (TTEthernet) is a breakthrough communication technology that combines the reliability of traditional Ethernet with the precision of time-triggered protocols. Designed to meet stringent safety requirements, this IP is fundamental in environments where fail-safe operations are absolute, such as human spaceflight, nuclear facilities, and other high-risk settings. TTEthernet integrates seamlessly with existing Ethernet infrastructure while providing deterministic control over data transmission times, allowing for real-time application support. Its primary advantage lies in supporting triple-redundant networks, which ensures dual fault-tolerance, an essential feature exemplified in its use by NASA's Orion spacecraft. The integrity and precision offered by Time-Triggered Ethernet make it ideal for implementing ECSS Engineering standards in space applications. It not only permits robust redundancy and high bandwidth (exceeding 10 Gbps) but also supports interoperability with various commercial off-the-shelf components, making it a versatile solution for complex network architectures.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
RapidGPT is a next-generation electronic design automation tool powered by AI. Designed for those in the hardware engineering field, it allows for a seamless transition from ideas to physical hardware without the usual complexities of traditional design tools. The interface is highly intuitive, engaging users with natural language interaction to enhance productivity and reduce the time required for design iterations.\n\nEnhancing the entire design process, RapidGPT begins with concept development and guides users through to the final stages of bitstream or GDSII generation. This tool effectively acts as a co-pilot for engineers, allowing them to easily incorporate third-party IPs, making it adaptable for various project requirements. This adaptability is paramount for industries where speed and precision are of the essence.\n\nPrimisAI has integrated novel features such as AutoReview™, which provides automated HDL audits; AutoComment™, which generates AI-driven comments for HDL files; and AutoDoc™, which helps create comprehensive project documentation effortlessly. These features collectively make RapidGPT not only a design tool but also a comprehensive project management suite.\n\nThe effectiveness of RapidGPT is made evident in its robust support for various design complexities, providing a scalable solution that meets specific user demands from individual developers to large engineering teams seeking enterprise-grade capabilities.
Credo Semiconductor excels in SerDes (Serializer/Deserializer) IP for custom ASICs, providing solutions that facilitate easy integration into various System on Chip (SoC) designs. The architecture of Credo's SerDes IP is based on a mixed-signal DSP approach that enhances performance while minimizing power and integration challenges. This architecture is especially beneficial for high-bandwidth data processing scenarios, making it an ideal choice for applications in AI, high-performance computing, and advanced telecommunication infrastructures.<br /><br />Their custom-built SerDes solutions stand out for the ability to handle tens and even hundreds of lanes, thanks to their innovative approach that seamlessly bridges the gap between core and analog logic deployment. These IPs are crafted to thrive even in mature process nodes, delivering remarkable efficiency in terms of power consumption and cost-effectiveness. By implementing these IPs, companies can ensure their systems are robust, future-proof, and capable of handling substantial data transmission tasks.<br /><br />Among the notable advantages offered by Credo’s SerDes IP is their adaptability with various signaling standards such as NRZ and PAM4, facilitating diverse data rate requirements up to 112G per lane. This flexibility not only aligns with current technological trends but also positions companies to swiftly adapt to future advancements in data communication technology, leveraging Credo's partnership with leading foundries and process nodes, such as TSMC's N3 and N5 technologies.
The Digital PreDistortion (DPD) Solution offered by Systems4Silicon is a versatile technology aimed at significantly enhancing the efficiency of RF power amplifiers. This advanced sub-system is scalable and adaptable to both ASIC and FPGA platforms, ensuring broad compatibility across various device vendors. The DPD solution meticulously enhances linearity, crucial for devices operating within multi-standard environments, such as 5G and O-RAN systems.\n\nDesigned to optimize the signal processing in transmission systems, this DPD technology allows for considerable power savings by enabling amplifiers to function more efficiently. Systems4Silicon’s approach ensures that the system can maintain its performance across different transmission bandwidths, which can scale to 1 GHz or higher. This makes it particularly valuable for large-scale and high-frequency applications.\n\nThe DPD technology's implementation is straightforward, providing a field-proven solution that integrates seamlessly with current infrastructures. Its adaptability is not merely limited to the hardware spectrum but extends to accommodate evolving communication standards, ensuring it remains relevant and effective in diverse market scenarios.
The AXI4 DMA Controller is a highly versatile IP core that supports multi-channel data transfers, ranging from 1 to 16 channels, depending on system requirements. Optimized for high throughput, this controller excels in transferring both small and large data sets effectively. It features independent DMA Read and Write Controllers for enhanced data handling with options for FIFO transfers to a diverse array of memory and peripheral configurations. This IP core offers significant flexibility with its programmable burst sizes, supporting up to 256 beats and adhering to critical boundary crossings in the AXI specification.
The EZiD211, also known as Oxford-2, is a leading-edge demodulator and modulator developed by EASii IC to facilitate advanced satellite communications. It embodies a sophisticated DVB-S2X wideband tuner capable of supporting LEO, MEO, and GEO satellites, integrating proprietary features like Beam Hopping, VLSNR, and Super Frame applications. With EZiD211 at the helm, satellite communications undergo a transformation in efficiency and capacity, addressing both current and future demands for fixed data infrastructures, mobility, IoT, and M2M applications. Its technological forefront facilitates seamless operations in varied European space programs, validated by its full production readiness. EZiD211's design offers a unique capability to manage complex satellite links, enhance performance, and ensure robust and reliable data transmission. EASii IC provides comprehensive support through evaluation boards and samples, allowing smooth integration and testing to meet evolving satellite communication standards.
The Digital Radio (GDR) from GIRD Systems is an advanced software-defined radio (SDR) platform that offers extensive flexibility and adaptability. It is characterized by its multi-channel capabilities and high-speed signal processing resources, allowing it to meet a diverse range of system requirements. Built on a core single board module, this radio can be configured for both embedded and standalone operations, supporting a wide frequency range. The GDR can operate with either one or two independent transceivers, with options for full or half duplex configurations. It supports single channel setups as well as multiple-input multiple-output (MIMO) configurations, providing significant adaptability in communication scenarios. This flexibility makes it an ideal choice for systems that require rapid reconfiguration or scalability. Known for its robust construction, the GDR is designed to address challenging signal processing needs in congested environments, making it suitable for a variety of applications. Whether used in defense, communications, or electronic warfare, the GDR's ability to seamlessly switch configurations ensures it meets the evolving demands of modern communications technology.
This IP core is engineered for applications where minimal latency is of paramount importance. The Ultra-Low Latency 10G Ethernet MAC features an optimized architecture to provide rapid data transmission and reception capabilities, ensuring that all processes occur smoothly and efficiently. It is tailored specifically for real-time operations where every millisecond counts, like high-frequency trading and real-time monitoring systems. By focusing on reducing latency, this Ethernet MAC core delivers exceptional performance, making it an excellent choice for demanding environments that cannot afford delayed communication. The core's architecture reduces overhead and maximizes throughput, leveraging Chevin Technology's advanced design expertise to minimize signal interference and processing delays. Its seamless integration with both AMD and Intel FPGA platforms makes it versatile for a variety of implementations across industry sectors. Moreover, it's designed to maintain optimal performance while managing high data loads, showcasing a consistent ability to handle extensive network traffic efficiently.
The HOTLink II Product Suite by Great River Technology is tailored for mission-critical avionics systems requiring robust data communication. It enables seamless data transfer and ensures consistent performance under high-stress operational environments. This suite incorporates advanced technologies to handle complex data streams effectively. It includes component options that enhance data throughput and communication efficiency, meeting stringent industry standards for avionics platforms. Designed with precision, the HOTLink II suite supports the integration and management of large datasets, ensuring that avionics systems can perform efficiently and reliably, crucial for modern aircraft and defense applications.
High-Speed SerDes for Chiplets is engineered to provide exceptional interconnect solutions tailored for chiplet architectures. This product offers ultra-low power consumption while maintaining high data transfer rates, essential for modern multi-die systems. By facilitating rapid communication between chiplets, it enhances overall system efficiency and performance. This SerDes solution is optimized for integration with a range of tech nodes, ensuring compatibility with various semiconductor manufacturing processes. Its design is focused on providing robust data integrity and reducing latency, which are crucial for efficient system operation in complex, integrated circuits. High-Speed SerDes addresses the growing demand for advanced interconnect solutions in chiplet architectures, making it an indispensable tool for developing next-generation semiconductor devices. Its ability to support high data throughput while keeping power use minimal makes it a standout choice in high-performance design environments.
This core is designed for high-performance applications requiring robust Ethernet connectivity with a high data throughput. The 10G Ethernet MAC and PCS solutions are developed to reliably handle speeds up to 10Gbps, optimizing the interface between Ethernet transmission and physical network layers. These IPs provide key functionality that helps maintain efficient data handling and transfer across networks, ensuring minimal latency and maximum productivity. Featuring refined architecture and robust design, this solution integrates seamlessly into FPGA frameworks, especially targeting Intel and AMD platforms. Its compatibility and reliability make it ideal for advanced networking tasks in a broad range of applications—from data centers to complex cloud infrastructures. The efficient management of data streams through this MAC and PCS combination ensures high-speed communication and responsiveness critical to high-demand environments. Its plug-and-play usability allows it to be quickly incorporated into existing systems, providing a flexible solution that maintains the scalability and performance needs of high-end systems. Additionally, Chevin Technology's expertise ensures that these cores come with comprehensive support tailored to enhance product integration and deployment efficiency.
The 2D FFT core is designed to efficiently handle two-dimensional FFT processing, ideal for applications in image and video processing where data is inherently two-dimensional. This core is engineered to integrate both internal and external memory configurations, which optimize data handling for complex multimedia processing tasks, ensuring a high level of performance is maintained throughout. Utilizing sophisticated algorithms, the 2D FFT core processes data through two FFT engines. This dual approach maximizes throughput, typically limiting bottlenecks to memory bandwidth constraints rather than computational delays. This efficiency is critical for applications handling large volumes of multimedia data where real-time processing is a requisite. The capacity of the 2D FFT core to adapt to varying processing environments marks its versatility in the digital processing landscape. By ensuring robust data processing capabilities, it addresses the challenges of dynamic data movement, providing the reliability necessary for multimedia systems. Its strategic design supports the execution of intensive computational tasks while maintaining the operational flow integral to real-time applications.
The Time-Triggered Protocol (TTP) designed by TTTech is an advanced communication protocol meant to enhance the reliability of data transmission in critical systems. Developed in compliance with the SAE AS6003 standard, this protocol is ideally suited for environments requiring synchronized operations, such as aeronautics and high-stakes energy sectors. TTP allows for precise scheduling of communication tasks, creating a deterministic communication environment where the timing of data exchanges is predictable and stable. This predictability is crucial in eliminating delays and minimizing data loss in safety-critical applications. The protocol lays the groundwork for robust telecom infrastructures in airplanes and offers a high level of system redundancy and fault tolerance. TTTech’s TTP IP core is integral to their TTP-Controller ASICs and is designed to comply with stringent integrity and safety requirements, including those outlined in RTCA DO-254 / EUROCAE ED-80. The versatility of TTP allows it to be implemented across varying FPGA platforms, broadening its applicability to a wide range of safety-critical industrial systems.
The DisplayPort 1.4 IP-core offered by Parretto B.V. is a compact yet potent solution for DisplayPort connectivity needs. Supporting a range of link rates from 1.62 to 8.1 Gbps, this IP-core accommodates varied setups with ease, including embedded DisplayPort (eDP) applications. It provides support for multiple lane configurations and both native video and AXI stream interfaces. The inclusion of Single and Multi Stream transport modes enhances its versatility for different video applications. Tailored for modern FPGA devices, the core supports a comprehensive video format range, including RGB and various YCbCr colorspaces. A standout feature is the secondary data packet interface, enabling audio and metadata transport alongside video signals. This makes it a full-fledged solution for video-centric applications, complemented by a Video Toolbox geared for video processing tasks like timing and test pattern generation. Parretto ensures the IP-core's adaptability by offering it with a thin host driver and API for seamless integration. The core is compatible with an extensive list of FPGA devices, such as AMD UltraScale+ and Intel Arria 10 GX. Customers benefit from the availability of source code via GitHub, promoting easier customization and deep integration into diverse systems. Comprehensive documentation supports the IP-core, ensuring efficient setup and utilization.
The AST 500 and AST GNSS-RF are multifaceted SOC and RF solutions designed for GNSS applications. They support a wide array of constellations such as GPS, GLONASS, NavIC, and others, in multiple frequency bands, enhancing navigation performance. These ICs integrate features like secure boots and data encryption, facilitating robust security measures crucial for sensitive data. The AST GNSS-RF is equipped with capabilities for L1, L2, L5, and S band reception, catering to high-fidelity signal requirements across various applications. The support for dual-band reception ensures that ionosphere errors are minimized, offering exceptional positioning accuracy.
Designed for seamless integration, High PHY Accelerators from AccelerComm encapsulate top-tier signal processing blocks critical for 5G solutions. Available as FPGA and ASIC ready IP cores, they are tailored for rapid deployment with minimal risk. These accelerators are supported by accurate simulation models and designed to use standardized interfaces for integration. Notably, they also provide support for space-hardened platforms, ensuring robust performance in diverse settings.
The Ethernet Real-Time Publish-Subscribe (RTPS) IP Core provides a comprehensive hardware implementation of the Ethernet RTPS protocol, facilitating real-time data sharing in network systems. It is designed to enable efficient and synchronized communications crucial in time-sensitive applications. Ideal for environments where timing precision and reliability are paramount, this core supports high-speed data exchanges with low latency performance. This ensures that critical data is published and subscribed to in real-time, meeting rigorous industry standards for communication efficiency. Moreover, the RTPS IP Core is constructed to seamlessly integrate into existing infrastructures, allowing for enhanced operations across diverse platforms while ensuring data flow consistency and system interoperability.
The RISCV SoC developed by Dyumnin Semiconductors is engineered with a 64-bit quad-core server-class RISCV CPU, aiming to bridge various application needs with an integrated, holistic system design. Each subsystem of this SoC, from AI/ML capabilities to automotive and multimedia functionalities, is constructed to deliver optimal performance and streamlined operations. Designed as a reference model, this SoC enables quick adaptation and deployment, significantly reducing the time-to-market for clients. The AI Accelerator subsystem enhances AI operations with its collaboration of a custom central processing unit, intertwined with a specialized tensor flow unit. In the multimedia domain, the SoC boasts integration capabilities for HDMI, Display Port, MIPI, and other advanced graphic and audio technologies, ensuring versatile application across various multimedia requirements. Memory handling is another strength of this SoC, with support for protocols ranging from DDR and MMC to more advanced interfaces like ONFI and SD/SDIO, ensuring seamless connectivity with a wide array of memory modules. Moreover, the communication subsystem encompasses a broad spectrum of connectivity protocols, including PCIe, Ethernet, USB, and SPI, crafting an all-rounded solution for modern communication challenges. The automotive subsystem, offering CAN and CAN-FD protocols, further extends its utility into automotive connectivity.
The TSN Switch for Automotive Ethernet is designed to address the needs of modern automotive networks by offering time-sensitive networking capabilities. This switch is tailored to manage Ethernet-based communication in vehicles, ensuring low-latency and reliable data transmission. It supports complex automotive network architectures, making it ideal for real-time communication requirements in vehicles. With its robust time-sensitive networking features, this switch is capable of guaranteeing data delivery within tight time constraints, a critical requirement for advanced driver assistance systems (ADAS) and autonomous driving. It integrates seamlessly within the automotive Ethernet ecosystem, providing scalability and integration flexibility. The switch is engineered to support the industry's move towards centralized vehicle networking, improving data throughput and reducing cabling complexity. The switch’s architecture supports multiple ports, allowing for the connection of various vehicle subsystems within a unified network framework. Implementing this technology can drastically improve the efficiency and reliability of in-vehicle communication systems. The TSN capabilities optimize network traffic management, ensure the prioritization of time-critical messages, and enhance the overall stability and predictability of automotive data flows.
The High Speed Data Bus (HSDB) IP Core offers a robust hardware implementation featuring PHY and MAC layers, optimized for high-speed data transmission. This IP core ensures seamless integration and supports F-22 compatible interface implementations, making it indispensable for advanced military communication systems. This core is instrumental in providing high throughput and low latency, crucial for applications that manage complex data transmissions. Its design caters to environments that require secure and efficient data handling, meeting the rigorous requirements of modern defense systems. The HSDB IP Core is particularly suited for situations where data integrity and transmission speed are pivotal, addressing the needs of platforms reliant on effective real-time communications. Its deployment aids in stabilizing operations across varied legacy and state-of-the-art systems, offering flexibility and reliability.
The Network Protocol Accelerator Platform (NPAP) is engineered to accelerate network protocol processing and offload tasks at speeds reaching up to 100 Gbps when implemented on FPGAs, and beyond in ASICs. This platform offers patented and patent-pending technologies that provide significant performance boosts, aiding in efficient network management. With its support for multiple protocols like TCP, UDP, and IP, it meets the demands of modern networking environments effectively, ensuring low latency and high throughput solutions for critical infrastructure. NPAP facilitates the construction of function accelerator cards (FACs) that support 10/25/50/100G speeds, effectively handling intense data workloads. The stunning capabilities of NPAP make it an indispensable tool for businesses needing to process vast amounts of data with precision and speed, thereby greatly enhancing network operations. Moreover, the NPAP emphasizes flexibility by allowing integration with a variety of network setups. Its capability to streamline data transfer with minimal delay supports modern computational demands, paving the way for optimized digital communication in diverse industries.
The PRACH IP Suite is a comprehensive solution optimized for 5G NR O-RAN Split 7.2X design. It includes a complete MATLAB model, RTL implementation, and a robust verification environment for bit-exact simulation and testing. This suite supports seamless integration and speeds up the development process with its 5G NR O-RAN compatibility, catering to the evolving needs of modern telecommunications infrastructure.
LightningBlu is a state-of-the-art multi-gigabit connectivity solution for high-speed rail networks, delivering continuous high-speed data transfer between trackside and train systems. This innovative solution works within the mmWave spectrum of 57-71 GHz and is certified for long-term, low-maintenance deployment. It seamlessly integrates with existing trackside networks to provide a stable, high-capacity communication bridge essential for internet access, entertainment, and real-time information services aboard high-speed trains. The LightningBlu system includes robust trackside nodes and compact train-top nodes designed for seamless installation, significantly enhancing operational efficiencies and passenger experience by providing internet speeds superior to traditional mobile broadband services. With aggregate throughputs reaching around 3 Gbps, LightningBlu sets the standard for rail communications by supporting speeds at which data demands are met with ease. Crucially, LightningBlu is a key component in transforming the railway telecommunications landscape, offering upgraded technology that enables uninterrupted and enhanced passenger digital services even in the busiest railways across the UK and USA. Through its advanced mmWave technology, it ensures that the connectivity needs of the modern commuter are met consistently and effectively, paving the way for a new era in transit communication.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The High-Speed Interface Technology by VeriSyno Microelectronics Co., Ltd. encompasses a range of connectivity solutions designed to meet the rigorous demands of modern applications. This suite includes versatile interfaces such as USB, DDR, MIPI, HDMI, PCIe, and SATA, each meticulously crafted to ensure seamless data transmission and robust performance across various technological landscapes. VeriSyno's high-speed interface solutions are built upon a robust framework that supports rigorous signaling protocols, ensuring consistency and reliability in high-bandwidth environments. These interfaces are optimized for diverse manufacturing processes, ranging from 28nm to 90nm, demonstrating flexibility and adaptability to next-generation design requirements. The technology facilitates customization, allowing clients to tailor interface attributes to specific application needs, thereby maximizing system efficiency. With a commitment to excellence, VeriSyno consistently updates its technology suite to incorporate latest advancements, ensuring clients benefit from leading-edge connectivity solutions.
The QUIC Protocol Core by Design Gateway is a high-speed, low-latency communication core designed to optimize network traffic in environments prone to congestion. It offers exceptional performance benefits over traditional protocols, leveraging the latest technology in secure and reliable data transmission.\n\nThis core is engineered to support high-speed environments, enhancing data throughput while reducing the likelihood of packet loss. It is particularly effective in networks with high congestion, where maintaining a seamless and efficient flow of data is critical. The QUIC Protocol Core's design focuses on minimizing latency, providing faster data exchange and enhancing overall network performance.\n\nIntegrating this protocol core into existing network infrastructure supports secure, encrypted data communication, vital for maintaining data integrity across various network environments. Its high-performance capabilities reduce overhead and improve application response times, making it indispensable for modern, high-speed data networks.\n\nBy incorporating the QUIC Protocol Core, businesses can optimize their network capabilities, ensuring secure, efficient, and reliable communications that are crucial for today's technology-driven communication systems.
The FCM1401 is a 14GHz CMOS Power Amplifier tailored for Ku-band applications, operating over a frequency range of 12.4 to 16 GHz. This amplifier exhibits a gain of 22 dB and a saturated output power (Psat) of 19.24 dBm, ensuring optimal performance with a power-added efficiency (PAE) of 47%. The architecture enables reduction in battery consumption and heat output, making it ideal for satellite and telecom applications. Its small silicon footprint facilitates integration in space-constrained environments.
The RWM6050 Baseband Modem is an innovative component of Blu Wireless's mmWave technology portfolio, architected to support high-bandwidth, high-capacity data communications. Designed in collaboration with industry leaders Renesas, this modem unit stands out for its efficiency and versatility, effectively marrying physical modem layers with advanced processing capabilities. The RWM6050 modem is instrumental in providing seamless data transmission for access and backhaul networks. Built to accommodate varying channelisation modes, the RWM6050 supports deep levels of customisation for different bandwidth requirements and transmission distances. It handles multi-gigabit throughput, which makes it ideal for expanding connectivity in urban or industrial areas with dense infrastructure requirements. From smart cities to complex transport systems, this baseband modem scales effectively to meet demanding data needs. Equipped with dual modems and integrated mixed-signal front-end capabilities, the RWM6050 offers a flexible solution for evolving communication infrastructures. Its design ensures optimization for real-time digital signal processing, beamforming, and adaptable connectivity management. The RWM6050 is a key enabler in unlocking the full potential of mmWave technology in a variety of settings, furthering connectivity innovations.
The SiFive Performance family is dedicated to offering high-throughput, low-power processor solutions, suitable for a wide array of applications from data centers to consumer devices. This family includes a range of 64-bit, out-of-order cores configured with options for vector computations, making it ideal for tasks that demand significant processing power alongside efficiency. Performance cores provide unmatched energy efficiency while accommodating a breadth of workload requirements. Their architecture supports up to six-wide out-of-order processing with tailored options that include multiple vector engines. These cores are designed for flexibility, enabling various implementations in consumer electronics, network storage solutions, and complex multimedia processing. The SiFive Performance family facilitates a mix of high performance and low power usage, allowing users to balance the computational needs with power consumption effectively. It stands as a testament to SiFive’s dedication to enabling flexible tech solutions by offering rigorous processing capabilities in compact, scalable packages.
The 10G TCP Offload Engine from Intilop brings a transformative approach to network protocol processing. Designed to handle TCP processing tasks, this engine ensures efficient data transmission by offloading TCP processing from the CPU, thus optimizing the resources available for other critical computing tasks. With features focused on reducing latency and increasing throughput, the 10G TOE is ideal for high-performance computing environments and data centers where speed and efficiency are paramount. The engine showcases Intilop's core expertise in delivering ultra-reliable and rapid networking solutions, providing support for multiple concurrent sessions with consistent low latency. Professionals in cloud services and enterprise networking will find the integration capabilities of the 10G TOE highly beneficial, as it supports a comprehensive suite of features that extend beyond traditional TCP processing, reinforcing security and operational efficiency.
OneNav presents the innovative L5-direct GNSS Receiver, a specialized component drawing focus to accuracy and reliability by operating independently of the L1 signal. Leveraging L5 Band signals, this receiver captures and maintains precise location data while ensuring protection against signal jamming. Incorporating a single RF chain, the system reduces redundancy and facilitates optimal antenna placement to enhance device designs in space-restricted environments. This approach critically lowers system costs while delivering robust, reliable location tracking ideal for wearables and IoT applications. The L5-direct receiver integrates seamlessly across multiple satellite constellations like GPS, Galileo, QZSS, and BeiDou, delivering accurate data regardless of environmental constraints. Its refinement in multipath error reduction through machine learning ensures the most precise data acquisition, even in dense urban landscapes. Enhanced with Application Specific Array Processor, the receiver accelerates signal acquisition without sacrificing time or power, ensuring reliable operation wherever used. Additionally, L5-direct GNSS stands out by optimizing power usage, with solutions designed specifically for extended battery life in ultra-low-power devices. Its adaptability allows for integration into diverse systems, serving industries with requirements across different geographies or use cases—from standalone GNSS ASICs to flexible modems and application processors. Featuring silicon-proven capabilities, such as a hot start fix in under one second and open-sky accuracy within 1.5 meters, L5-direct GNSS leads the way for next-generation technology in critical mission deployments.
ntRSE core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
Engineered to enhance data processing efficiency, the TCP/IP Offload Engine by Chevin Technology offers a significant boost in networking tasks by transferring processing workloads from CPUs to faster-processing hardware. This IP core supports 10 and 25Gbps data rates, allowing it to handle substantial data transfer needs frequently seen in distributed systems and cloud environments, reducing latency and freeing up CPU resources for other critical functions. Achieving optimal throughput and low latency, this offload engine is ideal for high-performance computing environments where speed and efficiency are non-negotiable. It excels in scenarios where large sets of data need to be managed efficiently, ensuring that network performance is not a bottleneck in overall system performance. Key to its operation is the ability to maintain consistent performance across various implementations, particularly those that leverage advanced FPGA platforms. This core streamlines networking tasks while simultaneously supporting scalability, making it a practical and efficient solution for enterprise-level networking projects.
CLOP Technologies' 60GHz Wireless Solution offers businesses an impressive alternative to traditional networking systems. Leveraging the IEEE 802.11ad WiFi standard and Wireless Gigabit Alliance MAC/PHY specifications, this solution achieves a peak data rate of up to 4.6Gbps. This makes it particularly suited for applications that require significant bandwidth, such as real-time, uncompressed HD video streaming and high-speed data transfers — operations that are notably quicker compared to current WiFi systems. The solution is engineered to support 802.11ad IP networking, providing a platform for IP-based applications like peer-to-peer data transfer and serving as a router or access point. Its architecture includes a USB 3.0 host interface and mechanisms for RF impairment compensation, ensuring both ease of access for host compatibility and robust performance even under high data rate operations. Operating on a frequency band ranging from 57GHz to 66GHz, the wireless solution utilizes modulation modes such as BPSK, QPSK, and 16QAM. It incorporates forward error correction (FEC) with LDPC codes, providing various coding rates for enhanced data integrity. Furthermore, the system boasts AES-128 hardware security, with quality of service maintained through IEEE 802.11e standards.
The Complete 5G NR Physical Layer solution by AccelerComm is meticulously optimized for 3GPP 5G NTN networks, aiming to enhance link performance with leading SWaP (Size, Weight, and Power) parameters. This solution supports a variety of applications including broadband, D2D (Direct to Device), and defense. With its openly licensable IP, available across multiple platforms such as arm processors, AI engines, and FPGA, it ensures the necessary flexibility for broad architecture compatibility. Complete reference systems facilitate early integration and testing, while additional consulting services provide expertise in early project phases.
The IPM-NVMe Device is crafted to empower developers to build custom hardware accelerators and SSD-like applications. Offering a high degree of customization, it acts as a foundation upon which cutting-edge applications can be realized. With its NVMe compliance, developers can integrate this IP to create high-performance storage solutions that are both adaptable and efficient. This module's versatility is exemplified by its support for enhanced data transfer rates, making it a suitable choice for environments demanding rapid data processing. The IPM-NVMe Device can be deployed in scenarios that require robust data handling capabilities while maintaining performance integrity. Designed with modularity in mind, the IPM-NVMe Device IP allows for the implementation of custom features, facilitating innovations such as new data management protocols, hardware accelerations, and more. Its deployment simplifies the challenging task of creating bespoke SSD solutions tailored to specific market needs and technological advancements.
SMPTE ST 2110 is a sophisticated protocol designed to facilitate the transport of media over IP networks, commonly used in broadcast and professional AV settings. This IP solution enhances the ability to transmit a variety of media types such as video, audio, and ancillary data via IP, leveraging the modularity to achieve optimal resource efficiency. Supporting an array of sub-standards, including uncompressed video (ST 2110-20) and compressed video (ST 2110-22), this IP bolsters transmission quality and reliability, ensuring consistent system timing and seamless traffic shaping. With its robust support for both gateway and synthetic essence operations, SMPTE ST 2110 enables effective integration with legacy systems and ensures a future-ready setup for the transmission of high-quality media content over IP. The core is highly configurable, allowing users to tailor features according to specific broadcast requirements while maintaining resource efficiency. By utilizing only necessary RTL logic, it minimizes overhead while offering a versatile solution for both professional AV equipment and broadcast systems. Integrated into an ecosystem of proven interoperable standards, this IP ensures smooth transitions between digital and traditional workflows, establishing itself as a pivotal component in AV-over-IP infrastructures. The design includes capabilities to handle various media types, making it adaptable to different operational needs. Nextera’s SMPTE ST 2110 IP is supported by a comprehensive reference design project, inclusive of necessary drivers and control software, enabling rapid system prototyping and deployment. Customers benefit from a well-documented setup that fosters swift development cycles and reduces time-to-market, underpinned by Nextera's emphasis on sustained performance and innovation within IP media experiences.
ntRSD_UF core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length, maximum number of parity symbols as well as I/O data width, internal datapath and decoding engines parallelism. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD_UF core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The core is designed and optimized for applications that need very high throughput data rates. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The eSi-Comms suite from EnSilica stands as a highly parametizable set of communications IP, integral for developing devices in the RF and communications sectors. This suite focuses on enhancing wireless performance and maintaining effective communication channels across various standards. The modular design ensures adaptability to multiple air interface standards such as Wi-Fi, LTE, and others, emphasizing flexibility and customizability.\n\nThis communication IP suite includes robust components optimized for low-power operation while ensuring high data throughput. These capabilities are particularly advantageous in designing devices where energy efficiency is as critical as communication reliability, such as in wearables and healthcare devices.\n\nMoreover, eSi-Comms integrates seamlessly into broader system architectures, offering a balanced approach between performance and resource utilization. Thus, it plays a pivotal role in enabling state-of-the-art wireless and RF solutions, whether for next-gen industrial applications or advanced consumer electronics.
Naneng Microelectronics offers a versatile Universal High-Speed SERDES capable of operating in a broad range of speeds from 1Gbps to 12.5Gbps. This SERDES is engineered to provide seamless and agile data transmission, underpinning critical communications infrastructure in various applications. The high-speed capabilities of this serializer/deserializer underline its suitability for high-performance networking solutions. Its flexible deployment options make it an ideal candidate for integration in a variety of system architectures, promoting a balance between speed and signal integrity. The design includes robust features to counter signal degradation and maintain the integrity of transmitted data, ensuring reliable operation across extensive data networks. Support for high data rates ensures this SERDES component meets and exceeds industry standards, delivering enhanced data throughput and supporting next-generation electronic systems. With adaptability at its core, the Universal High-Speed SERDES exemplifies comprehensive technological solutions in the semiconductor industry.
The UDP/IP Ethernet core by Enclustra is crafted to facilitate efficient and reliable data communication over Ethernet networks using the User Datagram Protocol (UDP). This IP core is integral for FPGA-based subsystems requiring seamless interconnectivity with other subsystems across network domains. By leveraging the simplicity and low overhead characteristics of UDP, this core ensures high-speed data transfer and is especially suited for applications where performance and simplicity are paramount, such as in embedded systems and networked control systems. It supports the transmission of data across various Ethernet configurations, thereby enhancing the flexibility and scalability of networking components. The core's implementation provides a reliable means of sending and receiving data packets across networks, making it a vital component for developers looking to create connected systems. Its integration into existing FPGA designs is straightforward, enabling quick deployment and consistent communication performance across Ethernet infrastructures.
This RF transceiver is a versatile solution designed for effective communication in the Sub-GHz frequency bands, specifically 433, 868, and 915 MHz. Ideal for global applications, it adheres to the IEEE 802.15.4-2015 standard, ensuring compatibility with many existing wireless systems. With a data rate capability ranging from 128 kbps for both Rx and Tx to over 3+ Mbps for transmission, it supports robust connectivity in various environments. The transceiver stands out with its high integration, featuring an on-chip RF subsystem that eliminates the need for external radio chips, simplifying system architecture. Its built-in voltage regulators and bandgap reference enhance ease of integration into system designs. Notably, this transceiver supports modulation schemes such as GFSK, BPSK, and O-QPSK, offering flexibility for custom protocol development. Designed to operate efficiently across process nodes, the transceiver supports a wide range of foundries, making it a versatile option for diverse applications. With a transmit power range from -20 to +8 dBm and sensitivity levels reaching down to -106 dBm, it is engineered to assure reliable long-range communication without relying on complex mesh network setups. This simplifies the deployment in scenarios like smart metering where indoor and outdoor connectivity is critical.
The JPEG Encoder is a versatile and efficient solution for image compression applications. This encoder is designed to handle high-quality image formats, supporting pixel depths of up to 12 bits. It excels in delivering low-latency performance, crucial for applications requiring fast image processing such as those found in machine vision setups. Its capability to function in standard FPGA environments makes it a cost-effective option for diverse projects. The encoder comes in different configurations, each tailored for specific needs. The L1 configuration offers a monochrome multiplex pipeline, capable of operating at a pixel clock rate of 150 MHz, ideal for Spartan6 platforms. For enhanced image quality, the L2 configuration supports dual-pipe processing for high-quality output like YUV422 at frame rates up to 60fps. This configuration can be optimized for higher pixel clocks, up to 200 MHz, on custom platforms. Beyond its encoding prowess, the JPEG Encoder integrates seamlessly within network environments, supporting UDP/Ethernet streaming. This feature is complemented by comprehensive reference designs for camera systems, ensuring robust performance across various platforms. Whether you need a standalone IP or an integrated part of a broader SoC solution, this encoder offers the flexibility and reliability needed in modern digital imaging applications.
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